Design of steel pipe length measurement system based on CCD technology

There is a process in the steel pipe finishing production line that requires measuring the length of each steel pipe. The automatic length measurement systems currently in use can be basically divided into two types: one is to use a steel pusher to push the stationary steel pipe forward a certain distance, and calculate the length of the steel pipe through an encoder that rotates synchronously with the steel pusher and a photoelectric sensor installed in sequence; the other is to use online length measurement, that is, to drive the axial translation of the steel pipe through a rotating roller, and use the movement of the friction wheel pressed on the steel pipe to drive the pulse encoder, and combine the photoelectric sensor to calculate the length of the steel pipe.
This study analyzes the measurement principle and physical implementation of online length measurement, using FPGA as the central processor to achieve high integration of the system; using the linear array CCD device TCDl206SUP as a photoelectric sensor to achieve high-precision measurement of the length of the steel pipe, and to achieve the transmission of the measurement results through RS-485 communication, which enhances the remote control performance and resource sharing of the system.

1 Measurement principle of the system
The object to be measured in the Henggang primary rolling mill is 130×130 continuous rolling billet, the total length of this billet is between 30 and 40 m, and the temperature is about 1 000℃. It is required to measure the total length in real time, and then use the computer to make the best measurement and guide the cutting in real time. In addition, it is also required to record the length of the segment after cutting. In view of the above requirements, this paper adopts the measurement scheme shown in Figure 1.

In the figure: K1 and K2 are two sets of photoelectric switches, CCD1 is used to measure the total length of the billet, and CCD2 is used to measure the segment length of the billet. When the billet hits the photoelectric switch K1 after cutting, the tail length of the billet is measured by the CCD1 camera as X0. Assuming that the left edge of the field of view from K1 to the CCD1 camera is L0, the total length is Ln+X0. After measuring the total length, after computer calibration, CCD2 controls the cutting length, and measures the segment length through CCD2. When the head of the billet hits K2, CCD2 starts measuring. Assuming that the length measured by CCD2 is X1, and the distance between K2 and the cut is L1, the segment length is L1+X1, and the segment length is measured and displayed online in real time. The process of measuring X0 and X1 is as follows: Since the measurement object is a hot-rolled billet, the temperature is about 1,000℃, and it is a luminous body itself. Therefore, the measurement object does not need external light source illumination. The photoelectric switch works actively. When the billet moves and blocks the signal emitted by the photoelectric switch, the photoelectric switch signal generates an external interrupt signal through the measurement control board, applies for external interrupt to the computer, controls the CCD camera to collect data, filters the collected results, performs binary processing, and performs a series of calibration and processing to obtain the length of the measured billet.

2 System composition and functions of each part
The measurement system is mainly composed of light source, CCD sensor, CCD drive circuit, FPGA programmable device, signal conditioning circuit, LCD display circuit, RS-485 communication circuit and keyboard input circuit. Its composition block diagram is shown in Figure 2.

1) FPGA (EP3C) FPGA is the core part of the system. On the one hand, it generates CCD drive signals and controls CCD sensors to complete data collection. On the other hand, it filters and calculates the input signals after A/D conversion by the conditioning circuit to realize data processing. Then, the data display and transmission are realized by controlling the LCD display circuit and RS-485 communication circuit. If necessary, its functions can be expanded. For example, when the segment length meets the ruler length, the scissors are controlled to cut and the cut segment length is recorded.
2) CCD sensor drive circuit This drive circuit is one of the key technologies in the application of CCD devices. It is mainly to generate drive timing pulses that meet the working conditions of the device. This system uses FPGA to realize the drive of the linear array CCD device TCDl206SUP.
3) Signal conditioning circuit The transfer part between the sensor and the microprocessor. Since the signal collected by the sensor is generally weak in energy, strong in interference, and is an analog signal, the main function of the conditioning circuit is to filter, amplify, and A/D convert the signal.
4) LCD display circuit realizes the data display function, so that the operator can understand the real-time measurement data and make corresponding processing.
5) RS485 communication circuit The communication distance between the measuring instrument on site and the host computer is far, so the system adopts RS-485 communication. RS-485 is the most commonly used in the current industrial field bus. This network structure is widely used due to its advantages such as simple hardware design, convenient control, low cost and high communication rate.

3 Function realization of each part of the system
3.1 CCD drive circuit
This drive circuit uses an independent pulse source. The clock generation circuit is composed of a crystal oscillator, which outputs a clock pulse with a frequency of 4 MHz. The clock pulse with a frequency of 1 MHz is obtained by a 4-frequency divider, and then the reset pulse φR with a duty cycle of 1:3 is synthesized by a pulse width modulator. The clock pulse φ1 is 0.5MHz, which is obtained by dividing the pulse signal by 8, and φ2 is generated by the inversion of φ1, as shown in Figure 3.

3.1.1 Implementation of frequency divider
This design requires 4 MHz clock pulses to be divided into 4 and 8 respectively. In FPGA design, the frequency divider can be designed using graphic input, using triggers or counters to achieve frequency division of different formats; it can also be designed using VHDL code input through different algorithms.
3.1.2 Implementation of pulse width modulator
The pulse width modulator mainly realizes the duty cycle of the pulse signal. From the TCDl206SUP driving timing diagram, it can be obtained that the frequency of the CCD reset pulse RS is 1 MHz and the duty cycle is 1:3. There are many ways to achieve 1:3 modulation. VHDL finite state machine (FSM) can be used for design. Set three different states of SO, S1, and S2. When the valid pulse arrives, the state machine switches from SO to S2 in sequence. In the S2 state, the state machine outputs a high level "1", and other states output a low level "O", thereby realizing a duty cycle 1:3 modulation. In the design of this system, the graphic input design method of QuartusⅡ is adopted. It is realized by using the XOR of two input signals. [page]

3.1.3 Implementation of pulse signal generator and inverter
The pulse signal generator is composed of a crystal oscillator, which outputs a clock pulse with a frequency of 4 MHz as the external clock of the FPGA, and the inverter can be implemented with a NOT gate circuit.
The symbols generated by the above parts are edited and connected using the Graphic Editor provided by QuartusⅡ. The overall module is simulated, and the result is shown in Figure 4. From the simulation results, the design requirements are met.

3.2 Signal conditioning circuit
The signal conditioner is an important part of the test system. It conditions the sensor output signal before the data acquisition system, thereby improving the performance and reliability of the data acquisition system. Common conditioning contents include amplification, isolation, filtering, channel switching and direct sensor conditioning. According to the design requirements, this signal conditioning circuit mainly amplifies, isolates and filters the signal of the CCD sensor. Taking into account the characteristics of weak signals, large interference and low frequency collected in industrial application systems, the amplifier circuit adopts a programmable amplifier circuit (PGA) composed of two AD526s and an IS0130 isolation amplifier circuit produced by the American BB Company. It has the advantages of good transient immunity and excellent anti-off-frequency noise performance, and can effectively suppress common-mode interference voltage. FP-GA changes the amplifier's amplification factor and improves the measurement sensitivity by controlling SWO, SW1 and SW2; the A/D converter uses AD7701. AD7701 is a single-chip 16-bit A/D conversion circuit with a linear error of only 0.001 5%. It is manufactured using LC2 process technology, has a built-in self-calibration circuit, and a serial output interface, which can be easily connected to a single-chip microcomputer. At the same time, it has the characteristics of low power consumption, high precision, and strong anti-interference ability, and is suitable for instruments and meters that require high precision, weighing and measuring, parameter detection, data acquisition, and other measuring equipment; the filtering circuit uses the programmable function of FPGA to generate the FIR filter core to achieve signal filtering. The signal conditioning schematic is shown in Figure 5.

3.3 Implementation of RS-485 communication
RS-485, as a serial communication interface, has the advantages of long transmission distance, high speed, good level compatibility, flexible and convenient use, low cost and high reliability. It is widely used in many fields such as intelligent management, online control, geological exploration, etc. RS-485 transceivers use balanced transmission and differential reception, that is, the driver at the transmitting end converts the TTL level signal into a differential signal output, and the receiving signal at the receiving end converts the differential signal into a TTL level. In the RS-485 interface, one line is defined as A, and the other line is defined as B. There is a signal ground C and an "enable" terminal. The "enable" terminal controls the disconnection and connection of the transmission driver and the transmission line. When the "enable" terminal is in effect, the transmission driver is in a high-impedance state, which is called the "third state", that is, it is different from the logic "1" and "0" third state. RS-485 has a strong ability to suppress common-mode interference and a high receiver sensitivity. It can detect a voltage of 200 mV, so the data transmission distance can reach more than 1 km.
The RS-485 interface connector generally uses a DB9 9-pin plug socket, and the RS-485 interface with the intelligent terminal uses a DB9 hole. The simplest RS-485 communication line circuit cable consists of two signal lines, and the interface generally uses shielded twisted pair transmission. The interface circuit between RS-485 and FPGA is shown in Figure 6.

4 System software implementation
The system uses Aherla's EP3C25E1448CN as the central processor. The entire measurement process mainly includes five different states: initialization, data acquisition (Data_Sample), data processing (Data_Processing), data display (Data_Display) and data transfer (Data_Transfers). The finite state machine method can be used for design, and its state transition diagram is shown in Figure 7. The development tool QuartusⅡ is used to compile and logically synthesize the VHDL source program and top-level circuit of each module, and various tests such as circuit error correction, verification, automatic layout
and wiring, and simulation are performed. Finally, the designed compiled data is downloaded to the chip.

5 Conclusion
This system uses programmable logic devices as a development platform to process data, high-precision CCD devices to realize data acquisition, and RS-485 communication to complete data transmission, making the entire system highly integrated, easy to debug, high in measurement accuracy, easy to realize remote control and information resource sharing, and has certain development potential.