MCU input/output (I/O) port

The MCS-51 microcontroller has four bidirectional 8-bit I/O ports, P0~P3 are three-state bidirectional ports, P1, P2, and P3 are quasi-bidirectional ports (when used as input, the port line is pulled to a high level, so it is called a quasi-bidirectional port).

Port P0 is a three-state bidirectional port, commonly known as the data bus port, because it is the only port that can be directly used for read/write operations on external memory. Port P0 can also be used to output the 8th address of the external memory. Since it is a time-sharing output, a latch should be added externally to latch this address data, and the address latch signal is ALE.

Port P1 is an I/O port for users. Users can use it as an I/O port line. Port P1 is a quasi-bidirectional port. Each bit is composed of a latch (SFR), an output driver, and an input buffer. Their pull-up resistors are actually not linear resistors, but are composed of field effect transistors, and each latch is composed of a D flip-flop.

Each I/O port has two reading methods: read latch and read pin. Each reading method has a corresponding instruction. The read pin instruction is generally an instruction with the I/O port as the original operand. When executing the read pin instruction, the three-state gate input port state must be turned on. For example: when reading the input state of port P1. The read pin instruction is: MOV A.P1

According to the structure of the I/O port and the control method of the CPU, after executing the read pin operation, the port latch state and the pin state should be the same. However, after writing a certain state to the port latch, whether the corresponding port pin presents a latch state depends on the connection of the external circuit. For example: when the base of a transistor is driven by an I/O port line, the transistor will be turned on after the bit latch of the port line is written with 1, and once the transistor is turned on, the base level is "0". If there is no read pin operation on the port line, the port latch and the pin state are inconsistent.