The Principle and Application of TWI Bus of AVR Series Microcontrollers

The AVR series of microcontrollers have integrated TWI (Two-wire Serial Interface) bus. This bus has the characteristics of I2C bus, that is, simple wiring, external hardware only needs two pull-up resistors, and 128 different devices can be interconnected using the clock line SCL and the data line SDA; it also supports host and slave operations, the device can work in transmitter mode or receiver mode, and the data transmission rate is up to 400 kHz. Because of these advantages, the TWI bus is favored by users.

Since the bus is very similar to the traditional I2C bus, many people mistakenly believe that the TWI bus is the I2C bus. In fact, this is just a simplistic understanding. The TWI bus is the inheritance and development of the I2C bus. It defines its own functional modules and registers. The definition of each register function is different from that of the I2C bus; and the TWI bus introduces a status register, making the TWI bus more flexible in operation and use than the I2C bus. In practical applications, since most microcontrollers do not have an integrated I2C bus, the control of the microcontroller is completed by simulating the timing of the I2C bus.

The TWI bus is integrated into the AVR series of microcontrollers, and its usage is more flexible than I2C. This article introduces the internal modules, working sequence and working mode of the TWI bus in detail with an example, aiming to correctly distinguish the TWI bus from the traditional I2C bus, and also has practical guiding significance for how to correctly use the TWI bus programming.

1 TWI internal module

TWI is composed of several sub-modules such as bus interface unit, bit rate generator, address matching unit and control unit, as shown in Figure 1. In the figure, SCL and SDA are TWI interface pins of MCU. The output driver of the pin contains a waveform slope limiter to meet the TWI specification; the input part of the pin contains a spike suppression unit to remove glitches less than 50ns. The bus interface unit includes data and address registers TWDR, START/STOP controller and bus arbitration hardware circuit. The bit rate generator unit is used to control the period of the clock signal SCL when TWI works in master mode, which is specifically set by the pre-scaling coefficient of the TWI status register TWSR and the bit rate register TWBR; when TWI works in slave mode, there is no need to set the bit rate or pre-scaling. The address matching unit will detect whether the address received from the bus matches the 7-bit address in the TWAR register. The control unit monitors the TWI bus and responds accordingly according to the setting of the TWI control register TWCR.

2 TWI working sequence

The TWT interface is byte-oriented and interrupt-based. All bus events (such as receiving a byte or sending a START signal, etc.) will generate a TWI interrupt. Since the TWI interface is interrupt-based, the TWI interface does not require application intervention during byte sending and receiving. The TWI interrupt enable TWTE bit of the TWCR register and the global interrupt enable of the SREG register together determine whether the application responds to the interrupt request generated by the TWINT flag. If TWIE is cleared, the application can only detect the TWI bus status by polling the TWINT flag; if the TWINT flag is set, it means that the TWI interface has completed the current operation and is waiting for the application to respond. In this case, the TWI status register TWSR contains the current TWI bus status value. The application can read the status code of the TWCR to determine whether the status code is correct at this time, and determine how the TWI interface should work in the next TWI bus cycle by setting the TWCR and TWDR registers. The typical working sequence of host byte transmission is shown in Figure 2.

3 TWI working mode

TWI can work in 4 different modes, namely, master transmission mode (MT), master reception mode (MR), slave transmission mode (ST) and slave receiver mode (SR). Even the same application can use several modes. For example, TWI can write data to TWI's EEPROM in MT mode and read data from EEPROM in MR mode. If there are other hosts in the system, they may send data to TWI, in which case SR mode can be used. The application decides which mode to use. Since the host transmission mode is mostly used in actual use, only the host transmission mode is introduced in detail, and the formats and states in other modes can be deduced accordingly.

In the master transmission mode, the master sends data to the slave. In order to enter the master mode, the START signal must be sent first; the format of the address packet that follows determines whether to enter the MT or MR mode. If SLA+W is sent, it enters the MT mode; if SLA+R is sent, it enters the MR mode. The format and status of the master transmission mode are shown in Figure 3.

4 TWI Programming Examples

The following is a specific example to illustrate how to program TW1 in actual applications. The main function of this program is to write data to PCA9554. If there is an error, it returns -1; otherwise, it returns 0. The parameter command is the command byte and data is the data to be written.

5 Conclusion

The AVR series of microcontrollers have internal programmable Flash and built-in EEPROM, and support JTAG interface on-chip debugging and programming of Flash, EEPROM, fuse bits and lock bits, making them the first choice for many microcontroller chips. At the same time, the AVR series of microcontrollers have an internal integrated TWI interface, which makes up for the defect that other types of microcontrollers rely on timing simulation to complete the work of I2C chips. This article introduces a method for programming the TWI bus through a detailed introduction to the TWI bus, which has practical guiding significance for the correct use of TWI.