AVR MCU Learning ATmega16 ADC

Conversion rate: The number of samples taken per second. Common units: SPS (times per second) KSPS (kilosamples per second) MSPS (millionsamples per second). The faster, the better.

Conversion precision: The number of significant digits (in binary) of the conversion result. Unit: bit

AVR's on-chip ADC:

Maximum conversion rate: 15kSPS

Maximum conversion accuracy: 10 bits

Features of AVR on-chip ADC:

10-digit precision

0.5 LSB nonlinearity

± 2 LSB Absolute Accuracy

65 - 260 μs conversion time

Up to 15 kSPS sampling rate at highest resolution

8 multiplexed single-ended input channels

7 differential input channels

2 differential input channels with selectable gains of 10x and 200x

Optional left-aligned ADC reading

ADC input voltage range of 0 - VCC

Selectable 2.56V ADC reference voltage

Continuous conversion or single conversion mode

Start ADC conversion by automatically triggering interrupt source

ADC conversion end interrupt

Sleep mode based noise suppressor

manual:

1. Initialize related registers

2. Read the conversion results

3. Smoothing Filter

4. Convert units

The conversion result is right-aligned by default, so the upper 6 bits are padded with 0s. Voltage gain is generally not used.

Related registers

First register: ADMUX

This is the multiplexer selection register, ADMUX 7 6 is the reference voltage source selection, there is a table

Generally, AVCC is unstable, so it is generally not used. Generally, 1 1 internal 2.56V is used.

The 5th bit: the conversion result is left-aligned. The default is right-aligned. Left alignment means placing it in the upper 10 bits and the lower 6 bits are padded with 0.

Generally, when left-alignment is used, only 8 bits of precision are needed. In this case, 8 bits of precision can be obtained by left-aligning and taking out the upper half byte.

Bit 4: Analog channel and gain selection bits There is a list of different combinations and gains, and we only need single-ended input now so set them all to 0.

Register 2: ADC Control and Status Register

Bit 7: ADC enable ADEN Set to start ADC

Bit 6: ADC starts conversion, starts ADC to start conversion

Bit 5: Auto-trigger enable. In many cases, it is necessary to sample analog signals cyclically. Auto-trigger sampling is very useful. For example, use a timer to sample once every 100MS. The trigger source will be discussed below.

Bit 4: ADC interrupt flag. This bit will be set after the conversion is completed.

Bit 3: ADC interrupt enable

Bit 2:0: Prescaler selection bit because it requires a clock. See the previous conversion timing diagram on page 194 below.

There is a table that can divide the crystal clock from 2 to 128.

50----200KHZ clock to get accuracy. Less than 10 bits can be higher than 200KHZ

Note: Normal conversion requires 13 ADCs (a little bit repeated with the above picture) 200KHZ /13 = 15.384 The highest value should be normal, so just press 200KHZ /13

Next, we calculate what range of clock it can provide to the ADC at 16MHZ.

The maximum is 16000 000 / 128 = 125.000, which means the minimum ADC clock is 125KHZ

Single conversion rate 125/13 = 9.6153846153846153846153846153846 9.615K This unit

Over 200KHZ the accuracy will decrease

The third register: ADCH ADCL two 8-bit registers

This register has two situations, which is determined by whether ADLAR is left-aligned or right-aligned.

The fourth register: special function IO register

This register is not dedicated to the ADC conversion register. Only bits 7, 6, and 5 are related to the ADC. Determines the ADC trigger source

All 0s are continuous conversion mode. That is, the conversion rate is 125/13, about 9.15

If the continuous mode is used, the conversion is completed and the interrupt is entered immediately, and then the interrupt immediately starts the next conversion. Therefore, the ADC conversion frequency is equal to the frequency of entering the interrupt.

The analog comparator is designed to have its own analog comparator function

External interrupt 0 An external interrupt triggers a conversion

The following are the interrupts of timers and counters.

The most commonly used mode is the continuous conversion mode.

adc.h key.h is the header file written by myself

First, buffer the data sampled by the ADC and temporarily store all 8 results.

Mean filter read_adc() returns read_BUF

voltile reads data from registers instead of cache every time

The STATIC variable is valid only in this file.

static voltile unsigned int adc_buffer[MAX_ADC_BUFFER]

MAX_ADC_BUFFER is a macro 9

void int_adc(void)

{

ADUMX |= (1<< unclear)|(1<< unclear) // is the reference voltage source 2.56V

ADCSRA |= (1<<) | (1<<) | (1<<) | (1<<) // ADC enable ADC test conversion continuous conversion interrupt enable 128 frequency division (the last 3 are set to 1)

}

unsigned int read_adc(void){

return adc_buff(0);

}

//ADC conversion completed interrupt

SIGNAL(SIG_ADC){

unsigned char i;

unsigned int temp sum =0;

temp = ADC ; //ADC data is given to temp Note that the result is right-aligned because we did not set left-align

for(i=1;i

//Here is a sum operation

adc_fuffer = adc_buffer[i+1]; //Move the elements forward one position sequentially

sum += ADC_BUFFER[i]; //add up

}

// Save the result of this conversion at the last position

adc_buffer() = temp;

sum + = adc_buffer(maxacdbuffer -1); //Sum of 8 results

The following is divided by 8, which is equivalent to shifting right 3 bits.

adc_buffer[[0] = adcbuffer >> 3

//This completes the smoothing filter of the ADC conversion result

}