51 MCU SNMP network management board driver

The SNMP network management board uses the RTL8019AS 10M ISA network card chip to access the Ethernet. The advantages of choosing it are: NE2000 compatibility, good software portability; simple interface without conversion chips such as PCI-ISA bridge; cheap price 2.1$/chip (my purchase price is 22 RMB/chip); sufficient bandwidth (for 51); will not be discontinued for a long time. 8019 has 3 configuration modes: jumper mode, plug-and-play P&P mode, and serial Flash configuration mode. In order to save costs, I removed 9346 and used X5045 as a flash drive to store MAC addresses and other configurable information. The P&P mode is used in PCs and is not used here. Only the jumper configuration mode is available. Its circuit design refers to the DEMO board drawings provided by REALTEK. It can be completed in one day, and the hardware design is relatively simple.

The software corresponding to this part of the hardware is the network card driver. The so-called driver refers to a group of subroutines that shield the underlying hardware processing details and provide hardware-independent interfaces to the upper-level software. The driver can be written as a subroutine and embedded in the application (such as I/O port operations and ISR under DOS), or it can be placed in a dynamic link library and dynamically loaded when used to save memory. In WIN98, in order to make the three modes of application programs of V86, WIN16, and WIN32 coexist, the concept of virtual machine was proposed. With the cooperation of the CPU, the system works in protection mode, the OS takes over I/O, interrupts, and memory access, and the application cannot directly access the hardware. This improves the system reliability and compatibility, but also brings about the problem of complex software programming. Any network card driver must be written in VXD or WDM mode. For the hardware side, it is necessary to handle virtual machine operations, bus protocols (such as ISA, PCI), plug-and-play, and power management; the upper-level software side must implement the NDIS specification. Therefore, it is quite complicated to implement a network card driver under WIN98.

The driver I am talking about here refers specifically to a set of hardware chip driver subroutines in real mode. From the programmer's perspective, the 8019 workflow is very simple. The driver writes the data packet to be sent into the chip in the specified format and starts the send command. The 8019 will automatically convert the data packet into a physical frame format for transmission on the physical channel. Conversely, after receiving the physical signal, the 8019 restores it to data and stores it in the chip RAM in the specified format for the host program to use. In short, the 8019 completes the mutual conversion between data packets and electrical signals: data packets <===> electrical signals. The Ethernet protocol is automatically completed by the chip hardware and is transparent to the programmer. The driver has three functions: chip initialization, packet reception, and packet transmission.

There is more than one Ethernet protocol, and I use 802.3. Its frame structure is shown in Figure 1. The sending and receiving operations on the physical channel all use this frame format. Among them, the preamble sequence, frame start bit, and CRC check are automatically added/deleted by the hardware and have nothing to do with the upper-layer software. It is worth noting that the format of the received data packet is not a true subset of the 802.3 frame, but as shown in Figure 2. Obviously, 8019 automatically adds three data members (4 bytes in total) of "receiving status, next page pointer, Ethernet frame length (in bytes)". The introduction of these data members facilitates the design of the driver and reflects the design idea of ​​​​software and hardware working together. Of course, the format of the sent data packet is a true subset of the 802.3 frame, as shown in Figure 3.

With the format of the send and receive packets, how to send and receive data packets? As shown in Figure 4, first store the data packet to be sent into the chip RAM, give the first address of the send buffer and the length of the data packet (write TPSR, TBCR0,1), and start the send command (CR=0x3E) to realize the 8019 sending function. 8019 will automatically complete the sending according to the Ethernet protocol and write the result to the status register. As shown in Figure 5, the receive buffer constitutes a circular FIFO queue. The two registers PSTART and PSTOP define the start and end pages of the circular queue. CURR is the write pointer, which is controlled by the chip, and BNRY is the read pointer, which is controlled by the host program. According to CURR==BNRY+1?, it can be judged whether a new data packet is received. The newly received data packet is stored in the RAM with the address indicated by CURR as the first address according to the format of Figure 2. When CURR==BNRY, the chip stops receiving data packets. If you have done FPGA design and used VHDL, you can imagine the working principle of hardware chips. Here, two 8-bit registers and a 2-input comparator are designed. When a data packet is received, the receiving state machine determines the next state based on the current state and the comparator result. If CURR=BNRY, it enters the stop receiving state; otherwise, CURR increases by 1. The 8019 data manual does not give the implementation method of the hardware state machine, and the description is also very brief. It is often necessary to infer the working process through experiments. For example, the ISR register is not only related to interrupts. When the receiving buffer overflows, if the ISR is not cleared (write FFH), the chip will stop receiving. Overflow often occurs when the traffic is large. At this time, if the ISR is not cleared, the network card chip will crash.

Now that we understand the principle of sending and receiving data packets, how are data packets written into and read from the chip RAM by the host? As shown in Figure 6, the host sets the remote DMA start address (RSAR0,1) and the number of remote DMA data bytes (RBCR0,1), and sets read/write in CR, and then the data in the chip RAM can be read from the remote DMA port register/written into the chip RAM.

What is local/remote DMA? As shown in Figure 7, "remote" refers to the CPU interface side; "local" refers to the hardware transceiver circuit side of 8019. There is no deeper meaning, it has nothing to do with distance, it is just to distinguish the two interface ends of the host and chip hardware. The DMA here is a little different from the DMA we usually talk about. The local DMA operation of RTL8019AS is completed by the controller itself, while its remote DMA is not without the participation of the host processor, and the data can be automatically moved to the memory of the main processor. Remote DMA means that the host CPU can read and write the chip RAM by giving the starting address and length, and the RAM address is automatically increased by 1 each time the operation is performed. Ordinary RAM operations have to send the address first and then process the data each time, which is slower.

Some high-end communication controllers have built-in MAC controllers, and their working principle is similar to that of 8019. For example, the CPM inside Motorola 68360/MPC860T has an Ethernet processor. By setting the BD table, the software and hardware can work together, and its buffer is larger and can be flexibly configured. The design of these communication controllers reflects the trend of software and hardware working together: software hardening (VHDL) and hardware softening (DSP). I hope everyone will pay attention to it!

As shown in Figure 7, the 8019 Ethernet controller is based on memory (16K dual-port RAM), and the local and remote controllers operate concurrently. This architecture meets the needs of data bandwidth. The 8019 has control, status, and data registers, through which the 51 microcontroller can communicate with the 8019. Due to the limited resources of the 51, do not copy memory blocks when implementing the TCPIP protocol stack. It is recommended that (1) use global structure variables to save only one copy of the data packet in the memory, and other packets that have not been processed in time are saved in the 8019's 16K RAM; (2) use the query method without interruption; (3) the server in the client-server model works in serial mode, and the concurrent mode is not suitable for the 51 microcontroller.

The allocation of the chip's internal address space is shown in Figure 8, where 0x00-0x0B (working in 8-bit DMA mode) is used to store the MAC address of this node, and the parity address content is placed repeatedly. For example: MAC address 0000 1234 5678 is stored in 0x00-0x0B as 000000001212343456567878, and the content of the single address and the double address is repeated. Generally, the content of the even address is used, which is mainly to adapt to both 8-bit and 16-bit DMA. The Prom content is read from the 93C46 when the network card is powered on and reset. If you don't use 93C46, don't use Prom. Then how to get the address of the network card after using 93C46? There are two methods, one is to read 93C46 directly, and the other is to read Prom. The MAC address of the network card is not determined by 93C46 or Prom, but by PAR0-PAR5 registers. Prom only saves the MAC address read from 9346 when powered on (if there is 93C46), nothing more.

The MAC address of a network card is not defined randomly. Its composition structure is shown in Figure 9. The Ethernet address is 48 bits and is uniformly allocated to network card manufacturers by IEEE. The address of each network card must be globally unique. The total length is 6 bytes. FF:FF:FF:FF:FF:FF is a broadcast address and can only be used in the destination address segment and cannot be used as a source address segment. Data packets with a broadcast address as the destination address can be received by all network cards in a local area network. The 32nd multicast flag of a legal Ethernet address must be 0. For example:

X0:XX:XX:XX:XX:XX

X2:XX:XX:XX:XX:XX

X4:XX:XX:XX:XX:XX

X6:XX:XX:XX:XX:XX

X8:XX:XX:XX:XX:XX

XA:XX:XX:XX:XX:XX

XC:XX:XX:XX:XX:XX

XE:XX:XX:XX:XX:XX

is a legal Ethernet address. The X above represents any one of 0-F.

address

X1:XX:XX:XX:XX:XX

X3:XX:XX:XX:XX:XX

X5:XX:XX:XX:XX:XX

X7:XX:XX:XX:XX:XX

X9:XX:XX:XX:XX:XX

XB:XX:XX:XX:XX:XX

XD:XX:XX:XX:XX:XX

XF:XX:XX:XX:XX:XX

It is a multicast address and can only be used as a destination address, not a source address. A multicast address can be received by a group of network cards that support the multicast address. Multicast addresses are mainly used in video broadcasting, remote wake-up (by sending a special data packet to make the network card generate an interrupt signal to start the computer), games (multiple people play games online in a local area network), etc.

The following are some specific multicast addresses:

Address range

01:00:5E:00:00:00---01:00:5E:7F:FF:FF is used for multicast of IP address. Other multicast addresses are not related to TCP/IP and are not introduced here.

The network card can receive data packets from the following three addresses:

The first type of data packet has the same destination address as its own network card address;

The second type of data packet has a destination address of FF:FF:FF:FF:FF:FF broadcast address;

The third type of data packet has a destination address that is in the same range as its own multicast address.

In Ethernet applications, if you want your data packet to be sent to only one network card, the destination address should be the other party's network card address;

If you want to send the data packet to all network cards, use the broadcast address as the destination address;

If you want to send a data packet to a group of network cards, use a multicast address as the destination address.

Other registers used:

CR---Command Register TSR---Transmit Status Register ISR---Interrupt Status Register

RSR---Receive Status Register RCR---Receive Configuration Register TCR---Transmit Configuration Register

DCR---Data Configuration RegisterIMR---Interrupt Mask RegisterNCR---Number of collisions during packet transmission

FIFO---After loopback detection, check the FIFO content

CNTR0---Frame synchronization error total counter

CNTR1---CRC error total counter

CNTR2---Total packet loss counter

PAR0-5---MAC address of this node

MAR0-7---Multicast address matching

Suggestion: Mark the register names in the diagram with the page number and address offset (e.g. BNRY page 0 0x03), print out the diagram, and program by looking at the diagram, which is intuitive and less prone to errors.

Note: The arrangement of the receive buffer, transmit buffer, and data storage area in the 16K dual-port RAM is determined by the user as long as it does not cause conflicts. The following source code implements only one of the allocation schemes.

Partial source program list:

struct ethernet{

unsigned char status; //receiving status

unsigned char nextpage; //next page

unsigned int length; //Ethernet length in bytes

unsigned int destnodeid[3]; //destination network card address

unsigned int sourcenodeid[3]; //Source network card address

unsigned int protocal; //Next layer protocol

unsigned char packet[1500]; //packet contents

};

void ne2000init() // ne2000 network card initialization

{

rtl8019as_rst();

reg00=0x21; //Select the register of page 0. The network card stops running because it has not been initialized yet.

delay_ms(10); //Delay 10 milliseconds to ensure the chip enters stop mode

//Put the chip in mon and loopback mode, disconnect from the external network

page(0);

reg0a=0x00;

reg0b=0x00;

reg0c=0xE0; //monitor mode (no packet receive)

reg0d=0xE2; //loop back mode

//Use 0x40-0x4B as the sending buffer of the network card, a total of 12 pages, which can just store 2 largest Ethernet packets.

//Use 0x4c-0x7f as the receiving buffer of the network card, a total of 52 pages.

reg01=0x4C; //Pstart receive buffer range

reg02=0x80; //Pstop

reg03=0x4C; //BNRY

reg04=0x40; //TPSR send buffer range

reg07=0xFF;/*Clear all interrupt flags*/

reg0f=0x00;//IMR disable all interrupt

reg0e=0xC8; //DCR byte dma 8-bit dma mode

page(1); //Select register of page 1

reg07=0x4D; //CURR

reg08=0x00; //MAR0

reg09=0x41; //MAR1

reg0a=0x00; //MAR2

reg0b=0x80; //MAR3

reg0c=0x00; //MAR4

reg0d=0x00; //MAR5

reg0e=0x00; //MAR6

reg0f=0x00; //MAR7

initNIC(); //Initialize MAC address and network related parameters

//Set the network card to normal mode and connect to the external network

page(0);

reg0c=0xCC; //RCR

reg0d=0xE0; //TCR

reg00=0x22; //Let the chip start working now?

reg07=0xFF; //Clear all interrupt flags

}

void send_packet(union netcard *txdnet,unsigned int length)//ne2000 packet sending subroutine

{//Send a data packet command, the minimum length is 60 bytes, the maximum length is 1514 bytes. The data packet to be sent must be stored in the txdnet buffer first.

unsigned char i;

unsigned int ii;

page(0);

if(length<60) length=60;

for(i=0;i<3;i++)

txdnet->etherframe.sourcenodeid[i]=my_ethernet_address.words[i];

txd_buffer_select=!txd_buffer_select;

if(txd_buffer_select)

reg09=0x40; //txdwrite highaddress

else

reg09=0x46; //txdwrite highaddress

reg08=0x00; //read page address low

reg0b=length>>8; //read count high

reg0a=length&0xFF; //read count low;

reg00=0x12; //write dma, page0

for(ii=4;ii reg10=txdnet->bytes.bytebuf[ii];

for(i=0;i<6;i++){ //Resend up to 6 times

for(ii=0;ii<1000;ii++) //Check if txp is low

if((reg00&0x04)==0) break;

if((reg04&0x01)!=0) break; // indicates successful sending

reg00=0x3E;

}

if(txd_buffer_select) reg04=0x40; //txd packet start;

else reg04=0x46; //txd packet start;

reg06=length>>8; //high byte counter

reg05=length&0xFF; //low byte counter

reg00=0x3E; //to sendpacket;

}

bit recv_packet(union netcard *rxdnet) //ne2000 packet receiving subroutine

{

unsigned char i;

unsigned int ii;

unsigned char bnry,curr;

page(0);

reg07=0xFF;

bnry=reg03; //bnry page have read read page pointer

page(1);

curr=reg07; //curr writepoint 8019 write page pointer

page(0);

if(curr==0)

return 0; //Error in reading process

bnry=bnry++;

if(bnry>0x7F) bnry=0x4C;

if(bnry!=curr){ //This indicates that there is a new data packet in the buffer

//Read the first 18 bytes of a packet: 4 bytes of 8019 header, 6 bytes of destination address, 6 bytes of source address, 2 bytes of protocol

//It is best to return to page0 in any operation

page(0);

reg09=bnry; //read page address high

reg08=0x00; //read page address low

reg0b=0x00; //read count high

reg0a=18; //read count low;

reg00=0x0A; //read dma

for(i=0;i<18;i++)

rxdnet->bytes.bytebuf[i]=reg10;

i=rxdnet->bytes.bytebuf[3]; //Reverse the high and low bytes of the length field

rxdnet->bytes.bytebuf[3]=rxdnet->bytes.bytebuf[2];

rxdnet->bytes.bytebuf[2]=i;

rxdnet->etherframe.length=rxdnet->etherframe.length-4; //Remove 4 bytes of CRC

//Indicates that the data packet read is valid

if(((rxdnet->bytes.bytebuf[0]&0x01)==0)||(rxdnet->bytes.bytebuf[1]>0x7F)||(rxdnet->bytes.bytebuf[1]<0x4C)| |(rxdnet->bytes.bytebuf[2]>0x06)){

// If the receiving status is wrong, or the next_page_start is wrong or the length is wrong, all data packets will be discarded

page(1);

curr=reg07; //page1

page(0); //Switch back to page0

bnry=curr-1;

if(bnry<0x4C) bnry=0x7F;

reg03=bnry; //write to bnry

return 0;

}

else{//Indicates that the data packet is intact. Read the remaining data

if((rxdnet->etherframe.protocal==0x0800)||(rxdnet->etherframe.protocal==0x0806)){

//The protocol is IP or ARP only.

reg09=bnry; //read page address high

reg08=4; //read page address low

reg0b=rxdnet->etherframe.length>>8; //read count high

reg0a=rxdnet->etherframe.length&0xFF; //read count low;

reg00=0x0A; //read dma

for(ii=4;iietherframe.length+4;ii++)

rxdnet->bytes.bytebuf[ii]=reg10;

}

bnry=rxdnet->bytes.bytebuf[1]-1;//next page start-1

if(bnry<0x4C) bnry=0x7F;

reg03=bnry; //write to bnry

return 1; //have new packet

}

}

return 0;

}