Design of Digital Scan Controller in Sweep Frequency Receiver

O Introduction
With the continuous development of modern communication industry, the frequency measurement range of signals is becoming wider and wider, and some fields have reached 110GHz. The superheterodyne method is used to convert the signal to a lower intermediate frequency through frequency conversion, and the frequency measurement range of 110GHz can be achieved at a relatively low cost, making superheterodyne swept frequency receivers widely used. In superheterodyne swept frequency receivers, the role of the scanning controller is to control and coordinate various hardware units so that various parts in the receiver are synchronized with the rapidly changing scanning local oscillator. The higher the control accuracy and the faster the control speed of the scanning controller, the higher the scanning accuracy of the receiver. At present, there are quite a few superheterodyne swept frequency receivers on the market that use analog scanning control methods, using scanning ramp voltage to synchronize various scanning hardware units. This control method has poor accuracy and requires the main control CPU to intervene in the scanning process in real time, making the scanning speed of the receiver very slow. In response to these problems, this paper provides a new method for designing a digital scanning controller. Using this method, our unit successfully developed a new type of microwave millimeter wave receiver in 2005, and its scanning control accuracy, scanning speed and other indicators have been greatly improved compared with previous receiver products.

1 Scanning control variables
The variables that generally need to be controlled during the scanning process of a superheterodyne swept-frequency receiver are: YIG oscillator frequency (or VCO frequency), YIG filter center frequency (or bandpass filter frequency), power compensation data related to the test frequency (such as flatness compensation data), etc.
The ideal YIG device tuning curve is a straight line (the tuning curve is a curve drawn based on the change in resonant frequency and coil current), but due to the influence of the magnetic properties of the magnetic material, the actual tuning curve is nonlinear. Similarly, since the amplitude-frequency response curves of various components in the receiver (such as mixers, filters, etc.) are nonlinear, the amplitude-frequency curve of the entire machine is also nonlinear.
In engineering, the multi-segment straight line approximation method is usually used to linearize the above curves, that is, to linearize the curves of each control quantity.

The line is divided into segments, and the control quantity curve is considered to be a straight line within the segment. As long as the position of each segment segment point is selected appropriately, the overall machine index can meet the design requirements.
By calculating the starting value, step value and number of steps of each segment control quantity (the end value minus the starting value and then divided by the step amount), the control quantity curve of this segment can be characterized. The superheterodyne sweep receiver contains a variety of control variables, so the starting value, step value and number of steps of the control quantity need to be calculated for each control variable. Since the control quantity curves are different, the number of straight line segments used to approximate the curve is also different. The more segmented lines are, the better the approximation effect and the higher the control accuracy. Therefore, before performing scanning control, the computer main control program should first determine the number of segments of each control quantity and the starting value, step value and number of steps in each segment, which are the input parameters sent to the scanning controller. In addition, in order to improve the control speed and avoid CPU intervention in the scanning process during the scanning process, when each control quantity changes segments, the designed scanning controller is required to actively read the segment change information of the next segment according to the control progress. Next, we will introduce in detail the composition and implementation of each unit in the digital scanning controller.

2 Composition block diagram and control timing
As shown in Figure 1, the scan controller includes: address decoding/data cache unit, RAM storage unit, operation unit, trigger unit, interrupt processing unit, step pulse generation unit and D/A output unit.

The basic flow of scanning control is as follows:
1) The program first calculates the number of segments of each control quantity and the starting value, step value, and number of steps of each control quantity in the segment.
2) Through the system bus, the program sends the above calculated data to the RAM in the scanning controller for storage.
3) The program controls the trigger unit to generate a global interrupt signal, and the interrupt processing unit notifies the operation unit to read the initial value of the first segment of each control quantity.
4) The program controls the trigger unit to generate an enable signal and controls the step pulse generating unit to generate a counting pulse. At this time, the operation unit starts to perform accumulation/subtraction calculations and the counter records the number of pulses generated. The output value of the accumulation/subtraction operator is converted into a voltage value through a D/A converter to control the relevant hardware circuit.
5) When the count value of the counter in the operation unit reaches the number of steps set in this segment, the operation unit generates an interrupt signal, which is recognized by the interrupt processing unit and notifies the module in the operation unit that has generated an interrupt to automatically read the initial value of the next segment from the RAM. The interrupt levels generated by the four modules in the operation unit are different. If multiple interrupts are generated at the same time, the interrupt processing unit will cache and sort the interrupts and process the interrupts with the highest interrupt level first.
6) When the next counting pulse arrives, the module that generates the interrupt in the operation unit will restart the accumulation/subtraction operation and count, repeating steps 4 and 5.
7) The trigger unit records the scan time. When the scan time reaches the preset value, the trigger unit controls the enable signal to be low, the registers are reset, and the scan process ends.

3 Module internal implementation
1) Address decoding/data cache unit The address decoding/data cache unit is connected to the external bus and receives data and control words belonging to this scan controller through decoding, including: reset control word, scan enable control word, count value of the counter in the trigger unit (used to calculate the scan time), count value of the counter in the step pulse generating unit (used to generate step pulses), and the control quantity DAC value to be stored in the RAM.
2) RAM storage unit
Stores the control quantity DAC value. If the address resources in the receiver are sufficient, the software can directly access the RAM through the address decoding/data cache unit. If the address resources in the receiver are limited, the entire RAM can be divided into several areas (segment addresses), each area corresponding to a control quantity. The segmented data of each control quantity are arranged in sequence and can be accessed through the offset address in the segment.
3) Arithmetic unit
The arithmetic unit includes a RAM data readback module, a counter, and an accumulator/subtractor module. The readback method of the RAM data readback module depends on the storage format of the data in the RAM; the counter determines whether to generate an interrupt by comparing the read step value with the current count value. In practical applications, the number of bits of the accumulator/subtractor is limited, and the number of bits of the calculated step DAC value may greatly exceed the number of bits of the operator. This requires designers to carefully select the effective length of the step DAC and appropriately intercept the DAC value so that the control error can be within an acceptable range. Under the triggering of the step pulse, the accumulator/subtractor module performs accumulation/subtraction operations on the initial value, and the number of bits of its DAC value output is equal to the number of bits of the selected DAC device.
4) D/A output unit
The D/A output unit is responsible for converting the accumulated/subtracted data into analog signal output. The timing of the D/A output unit is synchronized with the control pulse. If the scanning controller has few hardware resources, a D/A converter can be configured for each control quantity separately; otherwise, these control quantities can be cached first and then output through a D/A converter to reduce hardware costs.
5) Trigger unit
After receiving the scan enable control word, the trigger unit controls the enable end of the step pulse generating unit to be valid, and the step pulse generating unit starts to work, thereby making the entire scanning controller run. When the count value of the counter in the trigger unit is the same as the count value received for calculating the scan time, it indicates that the scan process has been completed. At this time, the trigger unit controls the enable end of the step pulse generating unit to fail, the step pulse generating unit stops working, and the scan process ends. In addition, before the scan starts, the trigger unit receives the control word to generate a global interrupt signal, and notifies the operation unit to call the initial DAC value of each hardware control quantity through the interrupt processing unit.
6) Interrupt processing unit
The interrupt processing unit determines the order of each module in the control operation unit according to the preset interrupt priority level. The interrupt processing unit consists of three parts: interrupt register, interrupt identification module, and reset processing module. The block diagram is shown in Figure 2.

The basic flow of scanning control is as follows:
1) The program first calculates the number of segments of each control quantity and the starting value, step value, and number of steps of each control quantity in the segment.
2) Through the system bus, the program sends the above calculated data to the RAM in the scanning controller for storage.
3) The program controls the trigger unit to generate a global interrupt signal, and the interrupt processing unit notifies the operation unit to read the initial value of the first segment of each control quantity.
4) The program controls the trigger unit to generate an enable signal and controls the step pulse generating unit to generate a counting pulse. At this time, the operation unit starts to perform accumulation/subtraction calculations and the counter records the number of pulses generated. The output value of the accumulation/subtraction operator is converted into a voltage value through a D/A converter to control the relevant hardware circuit.
5) When the count value of the counter in the operation unit reaches the number of steps set in this segment, the operation unit generates an interrupt signal, which is recognized by the interrupt processing unit and notifies the module in the operation unit that has generated an interrupt to automatically read the initial value of the next segment from the RAM. The interrupt levels generated by the four modules in the operation unit are different. If multiple interrupts are generated at the same time, the interrupt processing unit will cache and sort the interrupts and process the interrupts with the highest interrupt level first.
6) When the next counting pulse arrives, the module that generates the interrupt in the operation unit will restart the accumulation/subtraction operation and count, repeating steps 4 and 5.
7) The trigger unit records the scan time. When the scan time reaches the preset value, the trigger unit controls the enable signal to be low, the registers are reset, and the scan process ends.

3 Module internal implementation
1) Address decoding/data cache unit The address decoding/data cache unit is connected to the external bus and receives data and control words belonging to this scan controller through decoding, including: reset control word, scan enable control word, count value of the counter in the trigger unit (used to calculate the scan time), count value of the counter in the step pulse generating unit (used to generate step pulses), and the control quantity DAC value to be stored in the RAM.
2) RAM storage unit
Stores the control quantity DAC value. If the address resources in the receiver are sufficient, the software can directly access the RAM through the address decoding/data cache unit. If the address resources in the receiver are limited, the entire RAM can be divided into several areas (segment addresses), each area corresponding to a control quantity. The segmented data of each control quantity are arranged in sequence and can be accessed through the offset address in the segment.
3) Arithmetic unit
The arithmetic unit includes a RAM data readback module, a counter, and an accumulator/subtractor module. The readback method of the RAM data readback module depends on the storage format of the data in the RAM; the counter determines whether to generate an interrupt by comparing the read step value with the current count value. In practical applications, the number of bits of the accumulator/subtractor is limited, and the number of bits of the calculated step DAC value may greatly exceed the number of bits of the operator. This requires designers to carefully select the effective length of the step DAC and appropriately intercept the DAC value so that the control error can be within an acceptable range. Under the triggering of the step pulse, the accumulator/subtractor module performs accumulation/subtraction operations on the initial value, and the number of bits of its DAC value output is equal to the number of bits of the selected DAC device.
4) D/A output unit
The D/A output unit is responsible for converting the accumulated/subtracted data into analog signal output. The timing of the D/A output unit is synchronized with the control pulse. If the scanning controller has few hardware resources, a D/A converter can be configured for each control quantity separately; otherwise, these control quantities can be cached first and then output through a D/A converter to reduce hardware costs.
5) Trigger unit
After receiving the scan enable control word, the trigger unit controls the enable end of the step pulse generating unit to be valid, and the step pulse generating unit starts to work, thereby making the entire scanning controller run. When the count value of the counter in the trigger unit is the same as the count value received for calculating the scan time, it indicates that the scan process has been completed. At this time, the trigger unit controls the enable end of the step pulse generating unit to fail, the step pulse generating unit stops working, and the scan process ends. In addition, before the scan starts, the trigger unit receives the control word to generate a global interrupt signal, and notifies the operation unit to call the initial DAC value of each hardware control quantity through the interrupt processing unit.
6) Interrupt processing unit
The interrupt processing unit determines the order of each module in the control operation unit according to the preset interrupt priority level. The interrupt processing unit consists of three parts: interrupt register, interrupt identification module, and reset processing module. The block diagram is shown in Figure 2.

The interrupt processing process is as follows: First, the four interrupts are cached in four interrupt registers respectively. The interrupt register uses the FIFO storage unit to store multiple interrupts. Using the internal flag of the FIFO storage unit as the basis for logical judgment can simplify our design. Secondly, the interrupt identification module detects the empty flag of each FIFO storage unit. If the empty flag of any FIFO storage unit is 0, it means that an interrupt has occurred. Then the interrupt identification module will sort according to the interrupt priority level and generate a pulse to notify the data call module in the operation unit corresponding to the highest interrupt level to read the initial value of the next control amount from the RAM. Thirdly, after completing the reading task, the data call module returns a handler completion flag to the reset processing module. After receiving the handler completion flag, the reset processing module generates a read pulse according to the output interrupt category to the interrupt register with the empty flag of 0 and the highest interrupt priority. At this time, the empty flag of the interrupt register may change. Finally, the interrupt identification module detects again whether all the empty flags are 1. If not, the interrupt processing unit continues the above process until all the empty flags are 1. The interrupt processing process ends.
7) Step pulse generating unit
The step pulse generating unit contains multiple counters. The counting enable is controlled by the trigger unit, and the counter modulus is read from the address decoding/data buffer unit. At regular intervals, the step pulse generating unit generates a counting pulse as the clock of the accumulator/subtractor and is counted by the counter in the operation unit.

4 Design Example
Take a certain type of microwave millimeter wave receiver as an example. In this receiver, the system bus is designed as a serial bus, and the variables that need to be controlled are the YIG oscillator frequency, the YIG filter center frequency, the flatness compensation data, and the preselector bandwidth control voltage. The EplkSOQC208-3 chip of Altera is selected as the digital scanning controller chip, the IDT71V016SA20Y is used as the RAM storage chip, and the AD7538KR and DAC8412 are used as DAC conversion chips.
According to the measurement, the YIG oscillator frequency open-loop control accuracy reaches 5MHz (the frequency locking range of the receiver phase-locked loop can reach 80MHz), the YIG filter center frequency control accuracy reaches 3MHz (the minimum 3dB bandwidth of the YIG filter is 40MHz), the flatness compensation value error is less than 0.2dB, and the preselector bandwidth error is less than 2% of the bandwidth. The digital scanning controller uses a 60MHz clock as the external clock. In the busiest case (four interrupts arrive at the same time), the total time to complete the four interrupt processing is less than 5μs.
Through simulation and testing, the digital scan controller only uses about 70% of the resources in the FPGA, leaving room for future module expansion.

5 Conclusion
For the scanning controller hardware itself, we can improve the control accuracy by dividing the control curve into more segments and making it closer to the real curve; we can improve the control speed by selecting high-end FPGA chips and increasing the system working clock. However, in actual use, we must also comprehensively consider the impact of multiple factors such as the hardware performance (such as the hysteresis effect of the YIG device, the switching time of the mechanical switch, the response time of the intermediate frequency filter, etc.), the complexity of the software design, and the required performance indicators on the scanning control accuracy and speed, and reasonably select the number of segments and the working clock to maximize the potential of the receiver.