Design of Reconfiguration Controller Based on ARM+FPGA

Abstract: In order to meet the flexibility requirements of reconfigurable systems, this paper introduces the design of a reconfiguration controller with an "ARM processor + FPGA" structure, and proposes a method for the ARM microprocessor to configure the target programmable device in the system through the FPGA that simulates the JTAG interface. The hardware structure of the system design is given, and the timing requirements of JTAG in-system configuration of FPGA are introduced in detail. In this structure, how to use the IEEE JTAG1149.1 boundary scan test technology and the XSVF format configuration file that describes the JTAG bus standard to realize the in-system configuration of the target programmable device.
Keywords: JTAG interface; FPGA; reconfiguration; XSVF format

Reconfigurable technology refers to a design method that uses reusable software and hardware resources to flexibly change its own architecture according to different application requirements. Conventional SRAM FPGAs can be reconfigured. Using the principle of hardware reuse, the reconfigurable controller designed in this paper uses an ARM core microcontroller as the main controller and an FPGA chip as a coprocessor to work with the main controller. Users design different configuration schemes according to their needs in advance and store them in the memory inside the reconfigurable controller. After power-on, the reconfigurable controller can locate different design schemes in the target programmable device in a time-sharing manner according to needs, while keeping other circuit functions normal, achieving flexible configuration in the system and improving system work efficiency.

1 SVF format configuration file
Many embedded systems use programmable devices such as FPGA/CPlD. In these systems, the SVF format configuration file can be used to easily reconfigure the programmable devices through the microcontroller. Currently, the supporting software of programmable chip manufacturers can generate SVF format configuration files for programmable devices. Serial Vector Format (SVF) is a syntax specification for describing high-level IEEE 1149.1 (JTAG) bus operations. SVF was developed by Texas Instruments and has become a data exchange standard and is adopted by JTAG test equipment and software manufacturers such as Teradyne and Tektronix. Xilinx's FPGA and configuration PROM can receive programming instructions in SVF format through the TAP controller in the JTAG interface. Since the SVF file is composed of ASCII statements, it requires a large storage space and has a low storage efficiency, which is not suitable for embedded applications. In order to make full use of the limited storage space in embedded systems, SVF files are not directly used to program programmable devices in the system, but SVF files are converted into another binary format file with higher storage efficiency and stored in the data storage device. Xilinx provides the iMPACT tool for creating device programming files, which is included with the standard Xilinx ISETM software. The iMPACT software can automatically read standard BIT/MCS device programming files and convert them into compact binary XSVF format.
This design is based on the reconstruction controller of the "ARM processor + FPGA" structure. The FPGA in the reconstruction controller can control the JTAG interface of the target programmable device according to the commands transmitted by the ARM processor, and is responsible for interpreting the configuration file information in the XSVF format, generating programming instructions, data and control signals (TMs, TDI, TCK sequences) used by Xilinx devices to provide the required stimulus to the JTAG TAP controllers of the target programmable device, thereby executing the programming and (optional) test operations originally specified in the XSVF file. The TAP state machine in the target programmable device performs state transitions and scans instructions and data into the instruction register and data register of the boundary scan circuit inside the FPGA. Complete the configuration of the target programmable device once to achieve the functions required by the user at this time. In the next period, according to the user's new requirements, different schemes in the internal memory of the reconstruction controller can be called to reconfigure the target programmable device in the system, thus realizing hardware reuse and reducing costs.

2 Boundary Scan (JTAG) Principle
2.1 Basic Structure of JTAG Interface
JTAG (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible). Its working principle is to define a test access port (TAP) inside the device and test and debug the internal nodes through a dedicated JTAG test tool. TAP is a universal port. The external controller can access all data registers and instruction registers provided by the chip through TAP. Now the JTAG interface is also commonly used for chip online configuration (In-System Prograromable, ISP) to configure PLD, FLASH and other devices. JTAG allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, so that each device can be tested separately and configured in the system.

JTAG mainly consists of three parts: TAP controller, instruction register and data register, as shown in Figure 1. The standard JTAG interface has four sets of output lines: TMS, TCK, TDI, TD0, and an optional signal TRST.

TCK: JTAG test clock input. When TCK is kept at zero state, the test logic state should remain unchanged.
TMS: Test mode selection, controls JTAG state, such as register selection, data loading, test result output, etc. The signal appearing in TMS is sampled by the test logic and enters the TAP controller at the rising edge of TCK.
TDI: Test data input. Test data is sampled and enters the shift register (SR) at the rising edge of TCK.
TDO: Test data output. The test result is shifted out of the shift register (SR) at the falling edge of TCK. The output data and the data input to TDI should not be inverted.
TRST: Optional reset signal, valid at low level.
Xilinx devices accept programming instructions and test instructions using JTAG TAP. In the IEEE 1149.1 standard, common instructions for CPLD, FPGA and configuration PROM are: BYPASS instruction, bypassing (i.e. bypassing) a device in the boundary scan chain by directly connecting TDI to TDO with a 1-bit BYPASS register; EXTEST instruction, separating the device I/O pins from the internal device circuit to implement inter-device connection testing, which applies test values ​​through the device pins and captures the results; IDCODE instruction, returning a 32-bit hardware-level identification code used to define the component type, manufacturer and version number; HIGHZ instruction, making all device pins suspended in a high-impedance state; CFG_IN/CFG_0UT instruction, allowing access to the configuration bus used for configuration and readback; JSTART, providing a clock for the startup timing when the startup clock = JTAGCLK.
2.2 Tap state machine timing introduction
JTAG boundary scan testing is managed by the TAP controller of the test access port. The TMS, TRST and TCK pins manage the operation of the TAP controller, and the TDI and TDO bit data registers provide a serial channel. TDI also provides data for the instruction register, and then generates control logic for the data register. The control signals for selecting registers, loading data, testing and shifting out the results are controlled by two signals: test clock (TCK) and test mode (TMS). The test reset signal (TRST, generally active at low level) is generally used as an optional fifth port signal.
As shown in Figure 2, all JTAG-based operations must be synchronized with the JTAG clock signal TCK. All changes in test logic (such as instruction registers, data registers, etc.) must appear on the rising or falling edge of TCK. The key timing relationship is: TMS and TDI are sampled on the rising edge of TCK, and a new TD0 value will appear after the falling edge of TCK, so in general, the JTAG clock will not be too high.

Figure 3 shows the state diagram of the TAP controller defined by the IEEE 1149.1 standard. The TAP controller is a 16-state finite state machine that provides control logic for the JTAG interface. The TAP state transition is shown in Figure 3. The 1 or 0 on the arrow indicates the value of TMS at the rising edge of TCK (high level TMS = 1, low level TMS = 0). The state of TMS at the rising edge of the synchronous clock TCK determines the state transition process. There are two state change paths for the configuration data input to the device at the TDI end: one is used to shift instructions to the instruction register, and the other is used to shift data to the valid data register. The value of this register is determined by the currently executed JTAG instruction. When the TAP controller is in the instruction register shift (SHIFTIR) state, for each rising edge of TCK, the shift register in the instruction register group connected between TDI and TD0 shifts one position in the serial output direction.

When TMS remains at a high level, the TAP controller enters the "EXITl-IR" state at the rising edge of TCK; when TMS is at a low level, the TAP controller remains in the "instruction register shift" state.

3 Reconfiguration controller design
3.1 Hardware system composition
Its main function is to control the call of different schemes to configure the target programmable device according to different user requirements. It mainly includes ARM processor, FPGA, FLASH memory and external bus interface. The main functions of each functional component are as follows:
(1) ARM processor uses AT91FR40162S, and its main function is to control the FPGA simulating the JTAG interface to read the reconstruction scheme in the FLASH memory to realize the system configuration;
(2) FPGA coprocessor uses Xilinx's SPARTEN3AN series XC3S700AN-FGG484, which is an FPGA based on non-volatile storage and has its own PROM. It serves as a dual port between the external bus and the ARM controller. Its main function is to simulate the JTAG interface to realize the TAP controller timing, complete the parallel-to-serial conversion of the configuration scheme data and output it to the external bus;
(3) The FLASH memory capacity is 32M×16 b, which is used for the power-on boot of the processor and the storage of various reconstruction configuration schemes. Due to the large storage capacity required, the storage space of SPANSION's S29GL512P (32M×16 b) is used, with an access speed of 110 ns, which can achieve 25 ns fast page access and the corresponding 90 ns random access time, and FBGA packaging;
(4) External bus interface, which can use 1 RS 232 driver receiver to realize the interface with external communication;
(5) Test lines TCK, TMS, TDI and TD0 are used by the reconstruction controller to provide the required JTAG TAP stimulus to the target programmable device, respectively control the reconstruction configuration of multiple target FPGAs and feedback reconstruction information.
3.2 Working principle of reconstruction controller The
initialization work performed by ARM includes program update loading and running, FPGA parameter setting, etc.; FPGA sets the initial value of internal registers and logic states, clears internal buffer data, etc.
The schematic diagram of the reconstruction controller is shown in Figure 4. In the figure, the ARM processor reads the configuration scheme in the external FLASH through the ARM bus, performs parallel-to-serial conversion on it, and stores it in the FLASH memory; on the other hand, the FPGA that simulates the TAP controller in the reconstruction controller reads the configuration file from the ARM built-in FLASH memory, and executes the instructions issued by the ARM processor to interpret the file. The method of reconstructing the controller to interpret the binary file is as follows: under the control of the ARM processor, read a byte from the FLASH loaded with the configuration file, determine which JTAG instruction it is, and then perform specific processing according to the format of the instruction to generate TCK, TMs, TDI and TDO signals as the JTAG interface stimulus of the target programmable device, and connect them in series with the JTAG port of the target programmable device to form a daisy chain. Under the control of the ARM processor, the target programmable device is programmed in the system. The reconstructed FPGA is implemented by the Virtex-4 series FPGA of Xilinx that supports local dynamic reconstruction.

4 Conclusion
The reconfigurable controller introduced in this paper has the characteristics of high-speed processor core, small size, high integration, fast operation speed, large memory capacity, low power consumption, etc. of ARM microcontroller, and has the powerful parallel computing ability and convenient and flexible dynamic reconfigurability of FPGA, so that hardware information (configuration information of programmable devices) can be dynamically called or modified like software programs. For a specific target FPGA chip, under the drive of certain control logic, all or part of the logic resources of the chip are dynamically reconfigured, thereby realizing the time-division multiplexing of hardware, flexibly and quickly changing system functions, saving logic resources, and meeting large-scale application needs.