LED synchronous screen control system based on network port transmission and its FPGA implementation

Abstract: This paper introduces a design method of a full-color high-grayscale synchronous LED display screen control system based on FPGA and network port transmission. This design changes the inefficient and high-cost signal acquisition and transmission method in the traditional design, and uses real-time acquisition of DVI interface display signals and data transmission through the network port. It adopts highly integrated FPGA and large-capacity SDRAM, uses signal packet multiplexing technology to synchronously transmit display data and control data, and adopts new technologies such as high-efficiency grayscale slicing algorithm. It has the characteristics of low cost, large display area, stable display, and high refresh rate.
Keywords: DVI; FPGA; 100M network port; synchronous LED display screen control system; synchronous dynamic random access memory; grayscale slicing algorithm

The LED full-color synchronous control system has the advantages of high-performance real-time display, energy saving, and environmental protection, and has become an important medium for modern information release. This design changes the traditional design of collecting graphics card VESA signal interface and using parallel multiple buses to transmit data. Instead, it uses the acquisition DVI interface and transmits data through the network port, which not only saves costs but also improves transmission efficiency and quality. In addition, the design also adopts a series of new technologies, such as using highly integrated FPGA as the main control module, using large-capacity SDRAM instead of high-cost equal-capacity SRAM, using signal packet multiplexing technology to synchronously transmit display data and control data, and using high-efficiency grayscale slicing algorithms. The LED synchronous screen control system has the characteristics of low cost, large display area, stable display, and high refresh rate. It is a very competitive display control solution on the market.

1 System Principle and Structure
The overall system architecture is shown in Figure 1, which mainly consists of two parts: the sampling and sending board (STR) and the field control board (FRC). Through large-scale logic and other components, the display data output by the computer is collected in real time and synchronously, and after high-speed caching and format conversion, it is transmitted to the LED display screen through a large-capacity transmission channel, and finally converted into an LED scanning control signal, so as to realize the display of high-definition video, pictures, text and other program contents on the LED display screen.

1.1 Display signal acquisition
This design acquires high-definition display data signals from the DVI interface of the computer. DVI is mainly based on the TMDS (Transition Minimizerl Differential Signa-ling) technology to transmit digital signals. TMDS uses a coding algorithm to convert 8 tit (24-bit color RGB data, 8 bits for each color) into 10-bit data (including line field synchronization information, clock information, data DE, error correction, etc.) through minimum conversion coding, and uses differential signals to transmit data after DC balancing. It has better electromagnetic compatibility than LVDS and TTL, and can achieve long-distance, high-quality digital signal transmission with low-cost dedicated cables. This system uses a dedicated TFP401A chip. The TMDS signal output from the DVI interface of the computer display card is converted into a TTL-level RGB three-color separated data signal.
1.2 Display data format conversion
The display signal input by the DVI interface at high speed is serial grayscale data. Taking 24-bit color data as an example, the weight data of each color is 8 bits, that is, the grayscale level is 256 levels (28). The grayscale on the LED display is realized by controlling the lighting time of each LED, that is, the duty cycle. In order to realize different grayscales more efficiently, the design adopts the method of independent display of each weight on the full screen, that is, controlling the brightness of 1 to 8 weights on the entire screen.
The entire data format conversion process is realized by the two FPGAs on the acquisition and transmission board and the field control board and the SDRAM for data cache. Through a series of processes such as weight separation-caching-partition extraction-data reorganization, the scan data of the LED display is finally obtained.

1.3 Display data transmission
The amount of synchronous video signal data sent by the DVI interface is huge. In order to reliably output large-area, high-resolution, and high-grayscale video display data from the computer to the display screen, a reliable transmission medium is required. On the other hand, the distance from the computer to the LED display screen is generally tens of meters to hundreds of meters. The longer the transmission distance, the smaller the distance limit from the control room to the display screen, and the more flexible the engineering construction.
The interface chip in the design is implemented using RTL8208B. RTL8208B is an 8-port 10M/100M Ethernet transceiver chip produced by Realtek. In this design, the acquisition and transmission board STR only needs to use the transmission channel. The field control board FRC also only needs the receiving channel. Each Ethernet cable contains 4 pairs of twisted pairs, and only 2 pairs of them are used in 100M Ethernet. In this design, Gigabit Ethernet technology is used to use all 4 pairs of twisted pairs as transmission channels, so that each cable can transmit 400Mb/s of data, and 2 cables (8 channels) can transmit 800Mb/s of data. Table 1 is an analysis of the amount of data transmitted by the network port. In which, data amount = resolution × field frequency × 256-level grayscale data width.

From Table 1, we can see that a single network cable can transmit 1 024x512 full color or 1 024x768 two-color field frequency 30 Hz data; two network cables can transmit 1 024x512 full color or 1 024x768 two-color field frequency 60 Hz data.
1.4 LED display screen grayscale scanning
LED display screen is composed of multiple display modules, and the display interface is generally composed of the following signals: serial data signal: multiple groups of red, green, and blue signals; serial clock signal; CLK; serial latch signal: LATCH; output enable signal: OE; line coding signal (no line signal in static module): generally up to 16 lines of scanning, the line scanning signal is decoded by the decoder (74HCl38, etc.) on the display screen module.
In order to realize large-area display, the screen area of ​​LED display screen is generally very large, and the control data of the display screen is generally transmitted in serial, the control line is very long and easily interfered, and the signal frequency that can ensure stable transmission in large areas is limited. If the control area of ​​the system is increased, the general methods are: 1) Increase the clock frequency of the display control signal. But this increase is limited; 2) Reduce the refresh rate. Reducing the refresh rate will inevitably affect the display stability, and the effect is very poor; 3) Multiple controllers are processed simultaneously. Adding a scanning controller will inevitably increase the cost.
This design uses grayscale slicing to achieve high grayscale, large area, and high refresh rate display: calculated according to 256 grayscale levels (8 bits), the 8-bit weight data is D7 (128 weights), D6 (64 weights)...DO (1 weight) from high to low. Set a suitable serial clock for the output display. Increasing the parallel output RGB data signal group can increase the display area and meet the actual high-definition display effect. In this design, the actual control area is 1 024x768 pixels. Actual tests show that after using the grayscale slicing method, the brightness loss of the display is minimal, and a very stable video display can be achieved.

2 System Design
2.1 Functional Decomposition of Sampling and Sending Board
Figure 2 shows the overall architecture diagram of the sampling and sending board STR and the FPGA functional module diagram.

2.1.1 DVI interface
TFP401A inputs the following signals to FPGA after conversion: QE/QO sends 8-bit data for each group of signals: red, green and blue. This design uses TFP401A single-link TMDS mode; ODCK is the data clock; DE is data enable; VSYNC/HSYNC is the field synchronization signal and the line synchronization signal.
2.1.2 STR core control FPGA design
The core of the acquisition and transmission board is the high-speed logic device FPGA. The functional block diagram of FPGA is shown in Figure 2. FPGA collects data in real time and uses SDRAM cache to implement a series of high-speed synchronous data processing such as sampling, caching, and format conversion. At the same time, FPGA receives the control instructions of the computer through the CPU on the sampling and transmission board to adapt to different display screens and different application environments.
The functional modules of FPGA are described as follows:
1) Acquisition module ① Gamma correction: For different program sources and different display screens, different values ​​of gamma correction are required to obtain a display effect that is more in line with human vision and a clearer image. This design provides a gamma correction interface. Through the MCU on the sampling and transmission board, different gamma correction values ​​can be set according to the final display effect. After the data input is collected, it is converted into corrected display data. ②Weight separation and data reorganization: The input serial data is weighted and processed, and preliminary data reorganization is performed according to the display screen scanning mode set by the CPU.
2) The SDRAM control and arbiter system needs to process each frame of display data in real time, and use a large-capacity external memory as a buffer. Synchronous processing of input frame reception and output frame extraction.
In previous designs, two SRAMs (static memory) are generally used to store two frame signals independently, and the large-capacity SRAM is expensive. In this design, a single-chip SDRAM design is used. The price of SDRAM of the same capacity is much lower than that of SRAM, and the cost of the entire system will be further reduced by using a single-chip SDRAM; at the same time, the number of interfaces with the FPGA is reduced, the demand for the FPGA's I/O port is reduced, and the device selection is optimized.
The two-frame display signal is read and written in time-sharing, and the frame data currently being cached and the previous frame data currently being read are stored separately in different pages in the SDRAM. Since there is only one set of single-chip SDRAM control and data buses, an SDRAM control arbiter module is required to achieve seamless time-sharing bus switching control.
The acquisition module and the output module slice the data stream and convert it into small data blocks. After the data stream is sliced, the time each module occupies the bus is shortened. After accurately calculating the time each module occupies the bus and the longest interval required for occupying the bus twice, the appropriate size of the data stream slice is designed: 2 modules can realize seamless time-sharing occupation of the SDRAM bus.
3) Network port encoding output The output control module collects the data in the buffer SDRAM according to the scanning mode of the display screen, and converts and reorganizes it into a new network port serial transmission format. In addition to the display data that needs to be transmitted through the network port, in order to realize the remote setting of the field control board, the control parameters also need to be transmitted through the network port. Before the network port encoding, the display data packet and the control signal packet are time-division multiplexed, encoded by the network port encoder, and sent to RTL8208B for transmission.
4) Frame synchronization control data needs to synchronously process two frame signals on the sampling and sending board. In order to stably synchronize the frame signal of the output network port with the input DVI frame signal, the frame synchronization module locks the frame signals of the two clock domains together through synchronization instructions to achieve frame signal synchronization control and avoid display screen breaks.
2.2 Field control board function decomposition
Figure 3 is the overall architecture diagram of the field control board FRC and the FPGA functional module block diagram.

2.1.1 DVI interface
TFP401A inputs the following signals to FPGA after conversion: QE/QO sends 8-bit data for each group of signals: red, green and blue. This design uses TFP401A single-link TMDS mode; ODCK is the data clock; DE is data enable; VSYNC/HSYNC is the field synchronization signal and the line synchronization signal.
2.1.2 STR core control FPGA design
The core of the acquisition and transmission board is the high-speed logic device FPGA. The functional block diagram of FPGA is shown in Figure 2. FPGA collects data in real time and uses SDRAM cache to implement a series of high-speed synchronous data processing such as sampling, caching, and format conversion. At the same time, FPGA receives the control instructions of the computer through the CPU on the sampling and transmission board to adapt to different display screens and different application environments.
The functional modules of FPGA are described as follows:
1) Acquisition module ① Gamma correction: For different program sources and different display screens, different values ​​of gamma correction are required to obtain a display effect that is more in line with human vision and a clearer image. This design provides a gamma correction interface. Through the MCU on the sampling and transmission board, different gamma correction values ​​can be set according to the final display effect. After the data input is collected, it is converted into corrected display data. ②Weight separation and data reorganization: The input serial data is weighted and processed, and preliminary data reorganization is performed according to the display screen scanning mode set by the CPU.
2) The SDRAM control and arbiter system needs to process each frame of display data in real time, and use a large-capacity external memory as a buffer. Synchronous processing of input frame reception and output frame extraction.
In previous designs, two SRAMs (static memory) are generally used to store two frame signals independently, and the large-capacity SRAM is expensive. In this design, a single-chip SDRAM design is used. The price of SDRAM of the same capacity is much lower than that of SRAM, and the cost of the entire system will be further reduced by using a single-chip SDRAM; at the same time, the number of interfaces with the FPGA is reduced, the demand for the FPGA's I/O port is reduced, and the device selection is optimized.
The two-frame display signal is read and written in time-sharing, and the frame data currently being cached and the previous frame data currently being read are stored separately in different pages in the SDRAM. Since there is only one set of single-chip SDRAM control and data buses, an SDRAM control arbiter module is required to achieve seamless time-sharing bus switching control.
The acquisition module and the output module slice the data stream and convert it into small data blocks. After the data stream is sliced, the time each module occupies the bus is shortened. After accurately calculating the time each module occupies the bus and the longest interval required for occupying the bus twice, the appropriate size of the data stream slice is designed: 2 modules can realize seamless time-sharing occupation of the SDRAM bus.
3) Network port encoding output The output control module collects the data in the buffer SDRAM according to the scanning mode of the display screen, and converts and reorganizes it into a new network port serial transmission format. In addition to the display data that needs to be transmitted through the network port, in order to realize the remote setting of the field control board, the control parameters also need to be transmitted through the network port. Before the network port encoding, the display data packet and the control signal packet are time-division multiplexed, encoded by the network port encoder, and sent to RTL8208B for transmission.
4) Frame synchronization control data needs to synchronously process two frame signals on the sampling and sending board. In order to stably synchronize the frame signal of the output network port with the input DVI frame signal, the frame synchronization module locks the frame signals of the two clock domains together through synchronization instructions to achieve frame signal synchronization control and avoid display screen breaks.
2.2 Field control board function decomposition
Figure 3 is the overall architecture diagram of the field control board FRC and the FPGA functional module block diagram.

2.2.1 FRC core control FPGA design
The core control part of the field scanning board is also a FPGA. The FPGA receives the network port data in real time and uses SDRAM cache. After conversion, the output module realizes grayscale display and generates the control signal of the display screen. The functional modules are described as follows:
1) Network port decoder and data alignment and reorganization The RTL8208B of the field scanning board receives the data signal sent by the network port and sends it to the network port decoder module of the FPGA. This module is implemented by a state machine: after detecting the DV signal, H signal, and SSD signal in turn, the decoder starts to locate and extract the frame header signal, and determines whether it is a control frame or a data frame according to the data type in the frame header code, and extracts them respectively.
2) SDRAM control and arbitrator Similar to the acquisition and transmission board, the FPGA of the field control board also needs to process each frame of display data in real time, and uses the large-capacity external memory SDRAM as a buffer to synchronously process the input frame reception and output frame extraction. The SDRAM control arbitrator module realizes seamless time-sharing control.
3) Grayscale realization and scan conversion This module extracts the grayscale data in SDRAM and converts it into the control signal data of the display screen according to the description in Section 1.1. According to the scanning parameters in the control frame sent by the acquisition and sending board, the data sequence and control signal format of the scan output are adjusted to facilitate the flexible control of different types of LED display module groups. The LED grayscale scan output scan simulation signal is shown in Figure 4.

Figure 4 is the output original signal diagram. After adding shadow elimination (turning off the screen before switching lines to prevent the appearance of serial shadow signals is called shadow elimination), line adjustment, multi-display area interlacing (controlling a larger area), etc., the output signal is sent to the interface board matching the display interface after latching and driving to control the display of the entire LED display screen.
2.2.2 Output
driver The output driver latches and drives the scan signal output by the FPGA and sends it to the output interface. The external device then drives it through the adapter board and sends it to the LED display.

3 Conclusions
Large-scale logic has the characteristics of fast processing speed and large capacity. With the continuous updating of technology, it is developing rapidly towards higher capacity and lower unit cost. In the fields of real-time systems such as communications, the characteristics of FPGA are fully utilized in system design. FPGA is used as the core control module to integrate multiple control functions such as network control, large-capacity storage chip control, communication interface, peripheral device interface, signal acquisition interface, etc., which can simplify the system architecture and reduce the cost
of the entire control system and peripherals; and the streamlined system architecture avoids the defects of high system failure rate and easy mutual interference caused by matching multiple control devices. In the system design, the maturity of technology and the cost of the entire system engineering are fully considered. This design uses mature 100M network port chips and flexibly integrates Gigabit network technology, which greatly reduces the engineering cost and greatly improves the system stability. In actual testing and application, this control system has excellent parameters such as display stability and refresh frequency, whether it is indoor or outdoor display screen, and through technical means, it greatly increases the area of ​​single system control and reduces the cost. It has very strong market competitiveness through the simultaneous use of the software developed with it.