NiosII I2C Control IP and Its Application in Imaging System

Abstract: This paper introduces the working principle of an I2C control IP and its programmable registers in detail, and gives an application example of this IP in CMOS digital imaging. This example is designed based on the system-on-programmable chip (SOPC) technology. The system functions are realized by writing programs in the NioslI IDE, and verified by SignaITapII that comes with the QuartusII software. The results show that by selecting this IP core in the field of CMOS imaging, the system can fully utilize the advantages of SOPC technology, and has the characteristics of good scalability, flexible control, and short development cycle.
Keywords: SOPC; I2C control IP; CMOS

1 IP hardware structure and registers
1.1 IP hardware structure
The internal structure of IP is shown in Figure 1. It is mainly composed of five modules: baud rate clock register, register group controller, parallel I/O interface, I2C programmable interface, and I2C interface engine. The baud rate clock generator is used to generate the basic clock frequency of the I2C IP operation; the register group controller is used to set the register, and the setting data is transmitted to the module through the parallel I/O interface; the parallel I/O interface module is used to process the commands transmitted by the programmable interface module; the I2C programmable interface module is used to set the address of each register of the IP; and the I2C interface engine module executes the data transmission on the I2C bus.

1.2 Register Structure
The I2C control IP is mainly composed of 6 registers, as listed in Table 1. By reading and writing registers, the transmission of I2C bus data can be easily controlled, thereby realizing the communication between the NioslI processor and the device. The data register is used to store the data to be transmitted on the I2C bus; the baud rate generation module, the baud rate clock register and the clock register jointly determine the frequency of SCL on the I2C bus. The calculation formula of SCL is . Where System_clk is the system clock; Value is the value of the clock register; divider is the frequency division number corresponding to the value of the baud rate clock register (the difference between the register value and the frequency division number is 1. If the register is set to 0, the frequency division number is 1; if the register is set to 1, the frequency division value is 2). The detailed introduction of the local address register, control register, and status register is omitted - Editor's note.

2 Application of I2C control IP in imaging system
CMOS sensors are widely used in imaging systems. Most of these sensors have built-in I2C serial communication interface. This article takes MT9M011 as an example to introduce the application of I2C control IP in imaging system. MT9M011 sensor can be divided into two modes according to the number of read and write bits: 16-bit data read and write mode and 8-bit data read and write mode. Here, the exposure register is selected and the 16-bit read and write mode is used for operation. The timing is shown in Figure 2.

The upper 7 bits of the slave device address (write mode) and the slave device address (read mode) are the slave device address, and the 8th bit is the read/write control bit (R/W), which controls the data transmission direction.
Write data to the exposure register 0x09: The master device starts the transmission and then sends the slave device address (write mode) it wants to address. MT9M011 monitors the bus. When its address matches the transmitted slave device address, it responds with a one-bit acknowledgement signal. Then the master device sends the exposure register address. MT9M011 responds again. After writing 16 bits of data to the exposure register, the master device stops writing data. Every time 8 bits of data are transmitted, the slave device MT9M011 will generate a one-bit acknowledgement signal.
Read data from the exposure register 0x09: The beginning part is the same as the timing of writing data. After the master device sends the slave device address (write mode) and the register address, it needs to restart and send the slave device address (read mode) before it can read data from the register. Every time 1 byte of data is read, the master device will generate a 1-bit acknowledgement signal. After the 16-bit data is read out, the master device sends a 1-bit non-acknowledge signal and the transmission ends.

3 IP Application Examples
3.1 Hardware Design
This article uses I2C control IP to configure the image sensor MT9M01l registers in parallel. The hardware design is based on SOPC technology, integrating the 32-bit Nios II soft-core processor, SDRAM interface module, TIMER timer module (providing the frequency of signal sampling in SignaltapII), PI0 module and I2C control IP (configured as the master device) provided by the system component library into an FPGA. QuartusII top-level principle is omitted - Editor's note.
3.2 Software Design
There are two ways to write software: one is to operate the I2C control IP application programming interface (API) function; the other is to use the read and write functions provided by Altera to operate the registers. In order to increase the speed of system operation, the second method is used. The system software part is completed by writing C code in NiosII IDE.
The parallel configuration program for CMOS registers mainly includes the following two parts:
①IP initialization setting: including setting the baud rate, setting the local address register, and setting the clock register value.
②Select CMOS1 to read and write its registers; select CMOS2 to read and write its registers. Register selection exposure register.
The key code is as follows:



the checkBus function queries the BB of the status register to determine the busy/idle status of the I2C bus, and the checkProgres function queries the PIN of the status register to determine whether the bus data transmission is completed. In order to facilitate the observation of whether the read data is consistent with the written data, the program is usually included in the while statement.

4 Experimental verification
Burn the download file generated by the hardware system to the FPGA chip and run the C code program. Use the SignaItapII logic analyzer that comes with QuartusII to observe the data on the I2C bus. Figure 3 shows the obtained waveform. The signals from top to bottom are the I2C bus signals m_sclk_2, m_sda_2, m_sclk_1, and m_sda_1 on CMOS2/CMOS1. The first half writes 0x06 and 0x07 to CMOS1 and then reads it out; the second half writes the same number to CMOS2 and reads it out. This waveform meets the timing read and write requirements of the MT9M011 image sensor.

5 System Expansion
In applications that require multi-channel CMOS configuration, this I2C control IP can easily implement multi-channel parallel CMOS register configuration. For example, an 8-channel parallel CMOS configuration system: 8 CMOS sensor chips are soldered on the circuit board, and the enable is loaded in parallel to the 8 CMOS chips by controlling the 3-channel signal of the distributor. The 3-channel control signal and the enable signal are realized by controlling the PIO interface module of the SOPC system, and the transmission of the configuration data is completed under the control of the I2C control IP. The circuit board structure is simple and the system is easy to implement.

Conclusion
The I2C IP introduced in this article can be loaded into the SOPC system as a custom component, making the system design more flexible and having great potential for functional expansion. In the imaging system using CMOS image sensor, the I2C interface is widely used. This article gives an application example of this IP, which shows that the use of this IP has broad prospects and high application value.