The voltage reactive power controller is usually composed of a single-chip microcomputer system, which integrates data acquisition, data processing, control judgment and control output. This makes the single-chip microcomputer burden heavy, and is limited by the processing power of the single-chip microcomputer itself, and it is impossible to implement complex data processing and control strategies. Applying DSP chips to voltage reactive power controllers can effectively improve their performance.
The TMS320F24X series is a high-performance 16-bit fixed-point DSP launched by TI in the United States, specially designed for motor control and other control systems. TMS320F240 is a typical one of them. Its on-chip peripherals and powerful processing capabilities make it very suitable for voltage and reactive power controllers. This article focuses on the design and programming of the voltage and reactive power controller based on TMS320F240.
1 Design of voltage reactive power controller based on TMS320F240
1.1 Introduction to TMS320F240
TMS320F240 is mainly composed of three parts: CPU, memory and on-chip peripherals. Its main features are as follows:
It adopts an improved Harvard structure, has a separate program bus and data bus, uses a four-stage pipeline, and allows data to be transferred between the program storage space and the data storage space, thereby improving the operating speed and programming flexibility. The instruction execution speed is 20MIPS, and almost all instructions can be executed within a single cycle of 50ns.
· Memory addressable space 224K words (64K words of program space, 64K words of data space, 64K words of I/O space, 32K words of global space); 16K words of FLASH EEPROM on chip.
Dual 10-bit A/D converters, 16-bit input channels, 6μs conversion time. 3 timers/counters, 4 capture units, etc. in the event manager.
1.2 Controller Hardware Structure
The overall structure of the controller is shown in Figure 1, which consists of CPU, switch input, switch output, analog input, keyboard display and communication modules. The CPU module adopts a master-slave structure: the single-chip microcomputer (using INTEL's 80C196) is the master, completing the control of the peripheral circuit and processing the workflow of the entire controller; TMS320F240 is the slave, completing data acquisition, data calculation, etc. The single-chip microcomputer and TMS320F240 use dual-port RAM for communication.
A 10MHz crystal oscillator is connected between XTAL1 and XTAL2, and the system clock is 20MHz after the on-chip PLL clock module. The 16 A/D channels are divided into two groups: AD0~AD3 and AD8~AD11 are group 1, collecting the voltage and current of the high-voltage primary side of transformer #1 and the voltage signal of the low-voltage side; AD4~AD7 and AD12~AD15 are group II, collecting the power of transformer #2. The voltage and current of each phase on the high-voltage side are collected synchronously to ensure accurate calculation. The expanded 16K word external data memory is used to store the collected voltage and current. The expanded 2K×8-bit dual-port RAM is used to communicate with the single-chip computer (80C196). The use of dual-port RAM for communication has the advantages of simple program design and convenient and fast data transmission.
2 TMS320F240 programming
The program of TMS320F240 is written in assembly language, and its flow is shown in Figure 3. In the program initialization part, the internal registers of the chip are set. The general timer 1 is set to the continuous up-counting mode, and the code is as follows:
LDP #232
SPLK #1000000101000000h,T1CON
SPLK #0000000000101010b,GPTCON
SPLK #1563,T1PR ;set sample frequency=20000/2/1563=*kHz
The frequency is *kHz. The data acquisition part uses timer 1, and the data length is 128 points. In this way, for a 50Hz signal, the sampling can be guaranteed to be a full cycle. The A/D conversion is set to dual A/D synchronous sampling. For example, when sampling channels 0 and 8, the code for setting A/D is:
LDP #224
SPLK #1001100100000000b,ADCTRL1
SPLK #0000000000000101b, ADCTRL2
Harmonic analysis uses a base-2 128-point fast Fourier transform, taking the first 30 harmonic data and passing them to 80C196.
The voltage RMS, current RMS, active power and reactive power of each phase in the program are calculated using the following formulas (where N=128).
Voltage RMS:
Current effective value:
Active power:
Reactive power:
There is no square root operation instruction in TMS320F240. The square root in voltage and current calculation uses Newton's method. The Newton iteration formula of the root of the square root function f(x)=x2-c=0 is:
The speed of iterative convergence depends on the selection of the initial value of x. The closer the initial value x0 is to the true value, the faster the convergence speed. In the case of a political party, the voltage and current of the power grid, especially the voltage variation range, is not large, and the initial value is relatively easy to select.
Since the single-phase voltage and current are sampled synchronously, the power calculation is more accurate. The active power and reactive power of the three-phase circuit are the sum of their respective phases. When the circuit is three-phase symmetrical, three times the single-phase power can be used as the total three-phase power.
The communication between TMS320F240 and 80C196 is completed by dual-port RAM. In the dual-port RAM, a register unit is defined to store the command word DSP_MCU_CMD. The DSP reads and determines whether to perform sampling, whether to perform FFT, and whether to calculate the relevant power. After the DSP completes the instruction, it sets the corresponding position of the command word to 1; the 80C196 detects this bit and reads data from the dual-port RAM.
3 Experimental Results
A sine signal is generated by a signal generator, and after superimposing a 2.5V DC offset, it is input into two A/D synchronous acquisition channels (channel 0 and channel 8) for measurement experiments. Signal I is regarded as the voltage signal to be measured by the voltage reactive power controller; signal II is regarded as the current signal. The input signal waveform of Experiment 1 is shown in Figure 4, the frequency is 50.63Hz, the voltage U (signal I) leads the current I (signal II) by 27.6 degrees, and the experimental results are shown in Table 1; the input signal waveform of Experiment 2 is shown in Figure 5, the frequency is 49.69Hz, and the voltage U (signal I) lags behind the current I (signal II) by 44.5 degrees.
The application of TMS320F240 has greatly improved the performance of the voltage and reactive power controller, enabling the controller to respond to faults such as overvoltage, undervoltage, phase loss, harmonic over-limit, etc. At the same time, the data processing of the voltage and reactive power controller is separated from the peripheral control, which is conducive to the modular design of the system and improves the reliability of the system.
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