Design of high-precision and low-power ADC in touch screen controller chip

Abstract: In view of the high power consumption of existing touch screen controllers on the market, and the ADC is the core circuit of the touch screen controller, this paper designs an ADC circuit that works in two working modes: sleep/wake-up. When there is a touch event, the ADC is turned on and no wake-up delay is required, otherwise it is in sleep state. According to the parasitic capacitance, this paper optimizes the design of the DAC inter-stage coupling capacitor, which greatly improves the ADC accuracy. Practice shows that the chip can work in the voltage range of 2.5 V ~5.3V and the temperature range of -40 °C ~85 °C, the chip power consumption is less than 1mW, and 12-bit accuracy can be achieved. The circuit has the characteristics of high accuracy, low power consumption and small layout area, which has a guiding role in the optimization design of touch screen controllers.

Keywords: switched capacitor network; successive approximation analog-to-digital converter; coupling capacitor; comparator

Introduction

The ADC adopts a successive approximation (SAR) structure with a sampling rate of 125kHz and 12-bit accuracy. The capacitor charge redistribution D/A technology uses a charge proportional scaling sub-DAC combination, which greatly reduces the chip capacitor area and avoids the inherent DC power consumption brought by the resistor array structure. The ADC accuracy is improved by optimizing the design of the DAC inter-stage coupling capacitor value. The comparator uses a switched capacitor comparator with self-eliminating offset voltage.

According to the survey, the existing touch screen controller chips on the market mainly come from ADI (such as AD7843, AD7873, AD7877) and TI (such as ADS7843, TSC2046 , TSC2003). Their performance is compared, as shown in Table 1. Table 1 Touch screen controller chip performance comparison results By optimizing the ADC circuit design, the power consumption of the touch screen controller can be less than 1mW, which is lower than the power consumption of the existing chips in Table 1. Therefore, the focus of this design is to make the ADC work in two working modes of sleep/wake-up on the basis of meeting the working voltage and working temperature, so as to greatly reduce the power consumption. In order to achieve this goal, a voltage reference circuit module is designed in the chip to control the opening and closing of the ADC. Circuit Design and Analysis ADC Overall Structure Design SAR ADC includes sampling and holding circuit, comparator, DAC, successive approximation register, timing generation and digital control logic circuit. The analog input voltage (vin) is held by the sampling/holding circuit. The N-bit SAR ADC requires N comparison cycles, and the next conversion cannot be entered before the current bit conversion is completed. Therefore, this type of ADC can effectively save power and space. The design of DAC and comparator in this structure plays a key role in the conversion accuracy of the entire ADC. DAC Design DAC Structure Design Because in CMOS integrated circuits, manufacturing capacitors saves more chip area than manufacturing resistors, and there is no power loss on capacitors. In addition, the switched capacitor network can complete the sampling and holding function, saving a separate sampling and holding circuit. Therefore, this paper chooses to use a switched capacitor network to form a charge-scaling DAC. The charge-scaling DAC is mainly composed of a capacitor array arranged according to binary weighting. The capacitor is compatible with the CMOS process and has relatively high precision, so the charge-scaling DAC is easy to implement in the CMOS process. However, when its accuracy is improved, on the one hand, the required large capacitor leads to an oversized chip size, and the large capacitor requires a large charging current and a long charging time; on the other hand, the ratio of the highest-weighted and lowest-weighted capacitors becomes very large. The larger the ratio, the worse the capacitor matching. Therefore, high-precision DACs are usually implemented by low-precision DACs through capacitive coupling. One of the keys to the success of this coupling structure is to determine the coupling capacitor value. Only by selecting the appropriate coupling capacitor value can the weight relationship between each bit be guaranteed and D/A conversion be achieved, as shown in Figure 1. Figure 1 Implementation of charge-proportional scaling DAC combination Let the capacitance from point A to ground in Figure 1 be CA, and the scaling of DAC is achieved through capacitor CS. The series combination of CS and the LSB array must be connected to the left side of the MSB array. Therefore, it can be obtained that: During the layout design, in order to eliminate the influence of dielectric relaxation on conversion accuracy, eliminate charge diffusion and dielectric polarization effects, and reduce noise interference, an electrostatic shielding layer will be added to the upper plate of the capacitor and grounded. In order to eliminate substrate noise, the capacitor is made in the well and the well is grounded. The parasitic capacitance formed between the capacitor array plates and the shielding layer or well increases the parasitic capacitance value of the two plates of the coupling capacitor in the circuit, so that the influence of the parasitic capacitance must be considered when determining the coupling capacitance value.

Optimization design of coupling capacitance value between DAC stages

In Figure 1, CP1 and CP2 are parasitic capacitances from points A and B to ground, respectively. During the conversion process, the charges of A and B are conserved, so we can get:

C1 and C2 are the total capacitance of the low-weight and high-weight sub-DACs, respectively; CO1 and CO2 are the unit capacitance of the low-weight and high-weight sub-DACs, respectively; K=8, M=4. Solving the equations, we get the output voltage:

From the circuit parameters, we know: C02=4C, C01=2-2C=2-4C02, so:

Taking the high-weight DAC as the reference, the output should have the following expression:

Comparing equation (4) and equation (5), we can get:

Comparing equation (4) and equation (5), we can get:

Analysis of coupling capacitance formula (6) shows that the coupling capacitance is related to the low-weight parasitic capacitance, but not to the high-weight parasitic capacitance. The parasitic capacitance of the high-weight DAC does not affect the proportional relationship between the high and low weights, but only affects the absolute value of the final output voltage. From the output expression (5), we can see that the high-weight parasitic capacitance appears in the denominator, which will reduce the absolute value of the output, so the high-weight parasitic capacitance value should be minimized. The low-weight parasitic capacitance will also reduce the absolute value of the output, but this effect is very small, and compared with the effect of the high-weight parasitic capacitance, it can be almost ignored. According to equation (6), the low-weight parasitic capacitance appears in the numerator of the coupling capacitance expression, so the larger the low-weight parasitic capacitance, the larger the coupling capacitance value. By increasing the coupling capacitance value, the influence of the low-weight parasitic capacitance can be eliminated.

Parasitic capacitance is usually formed by the capacitor plate and the shielding layer or well, so the parasitic capacitance is related to the size of the high and low-weight parasitic capacitance. Therefore, in order to reduce the impact of high-weight parasitic capacitance on the output voltage, parasitics should be minimized during layout design.

After comprehensively considering the input capacitance requirements and capacitance matching accuracy, a dual poly capacitor in the N well is selected. The unit capacitance is 400fF, and the weight capacitor adopts a unit capacitor parallel structure to improve matching. A central symmetrical layout is adopted, and metal2 is covered on the capacitor as an electrostatic shielding layer; both the N well and metal2 are grounded. Parasitic capacitance mainly includes parasitic capacitance between the upper plate of the capacitor and metal2, and between the trace and metal2. Although the parasitic capacitance of the upper 4-bit sub-DAC does not affect the proportional relationship between the weights, it will reduce the output voltage value, so that a higher-precision comparator is required. Therefore, the metal2 covering the upper 4-bit sub-DAC capacitor is opened to reduce its parasitic capacitance.

Comparator design

Since the DAC module uses a switched capacitor network, a switched capacitor comparator that can eliminate DC offset voltage will be designed here. The switched capacitor comparator uses a combination of switched capacitors and open-loop comparators. Its advantage is that the differential signal can be compared with a single-ended circuit, and the DC offset voltage of the open-loop comparator can be automatically zeroed.

This paper uses the structure shown in Figure 2 to design the switched capacitor comparator in the SAR ADC.

Figure 2 Switched capacitor comparator circuit diagram

When the switch φ1 in Figure 2 is closed, the input offset is stored in the capacitor C connected in series with the input, and the capacitor C will automatically zero the input offset voltage VOS of the comparator. The capacitor CP represents the parasitic capacitance of the comparator input to the ground. At the end of the φ1 phase cycle, the voltages on C and CP are:

When switch φ2 is closed,

If CP is less than C, the above formula can be simplified as follows:

Therefore, the difference between voltages V1 and V2 is amplified by the gain of the comparator, and the latch behind generates a logic level based on the output of comparator A, outputs Vout, and the DC input offset voltage is automatically calibrated to zero.

The comparator A circuit is implemented as shown in Figure 3.

Figure 3 Self-canceling offset voltage comparator circuit implementation scheme The

final offset voltage of the N-level comparator can be expressed as:

Among them, A1~AN are the amplification factors of each stage, and VOSL is the offset voltage of the latch. The value is determined according to the gain requirements of the entire circuit and the intensity of the offset suppression requirements. Here, N=4.

The comparator consists of a three-stage differential amplifier and an output stage. The tubes M1, M2, M3, and M4 are turned on during the sampling period. By charging the capacitors C1, C2, C3, and C4, the static operating points of the second, third, and fourth differential amplifiers are fixed. The tubes M0~M4 are not turned on during the comparison conversion period. Since during the sampling period, the differential input terminals of each stage are connected to the static operating point voltage, which is equivalent to the AC ground, the output caused by the offset voltage is stored on the capacitors C1, C2, C3, and C4. When comparing, the input voltage is input in series with the offset voltage stored on the capacitor, so that the offset voltage at the input end is not amplified and output by each stage, thereby reducing the impact of the offset. The output stage consists of a differential amplifier that converts a double-ended terminal to a single-ended terminal and two NOT gates, and its function is equivalent to the aforementioned latch.

The working clock of the comparator is fCLK=2MHz, so the current provided by the current source should be relatively large. The tubes M5, M6, M7, and M8 act as current sources, and the switches are controlled by vbias to determine the DC bias of the circuit. vbias is the output of the comparator voltage reference circuit.

Design of voltage reference circuit

Since the power supply voltage VCC in the comparator circuit varies from 2.5V to 5.3V, the variation range is large. Therefore, for the comparator, there are not many DC operating points that make all tubes in saturation. When the power supply voltage changes, it is hoped to obtain a stable DC bias current, that is, to provide a stable reference voltage for the bias tubes M5, M6, M7, and M8 in Figure 3. The ideal reference current or voltage is independent of power supply and temperature changes, so the bootstrap reference technology is used, and the design is shown in Figure 4.

Figure 4 Threshold reference circuit

In Figure 4, tubes M5 and M6 make the currents I1 and I2 equal. I1 flows through tube M3 to generate voltage VGS3, and I2 flows through R to generate voltage I2R. Because these two voltages are connected together, an equilibrium point is determined, denoted by Q. The equation describing this equilibrium point is:

Since I ₁ =I ₂ =I _Q , we can solve:

First, I1 and I2 do not change with VCC as a function of VCC, so the sensitivity of IQ to VCC is basically zero, and a reference voltage is obtained by acting on a resistor.

However, there are two possible balance points in Figure 4. One is at Q and the other is at the origin. In order to avoid the circuit choosing the wrong balance point, there must be a startup circuit. The dotted box in Figure 4 is the startup circuit. The start-up circuit is turned on and off by digital signals AN1 and AN2. In order to control power consumption, the startup circuit will be turned off immediately after it is turned on.

The comparator circuit is controlled by the signal sel-y switch, that is, when sel-y=1, the comparator is turned off, and when sel-y=0, the comparator is turned on, so that the ADC works in two working modes: sleep/wake-up. When there is no touch event, the DC power consumption is greatly reduced.
Layout implementation and circuit simulation analysis

As shown in Figure 5, the layout is implemented using SMIC 2P2M 0.35μm CMOS process with an area of ​​1600x1700um2.

Figure 5 Layout design results of touch screen controller

Spectre and Spectre Verilog simulation tools in Cadence environment are used for simulation. The parasitic parameters of the layout are extracted, and the parasitic capacitance values ​​of points A and B in Figure 1 are 212.11fF and 278.53fF respectively. According to formula (6), the optimized coupling capacitance value CS is 1.72pF.

In order to measure the DNL and INL of the ADC, a ramp signal is added to the ADC. The text file of the digital code can be output from the simulation diagram, and the file can be used to draw and calculate its DNL and INL values ​​through the Matlab program. The drawing result is shown in Figure 6. The calculated DNL is 1/4LSB and the INL is -1LSB.

Figure 6 ADC full range simulation diagram As

can be seen from Figure 6, the ADC outputs 4096 steps, that is, a 12-bit A/D conversion is completed.

The power consumption of the SAR ADC is tested, and the test results are shown in Table 2.

Table 2 SAR ADC power consumption test results under different voltages

Conclusion

By analyzing the influence of parasitic capacitance on coupling capacitance in the charge scaling DAC combination structure, an optimization design method for coupling capacitance value is given. Through the switch capacitor comparator structure, the offset voltage of the comparator is eliminated. The optimized SAR ADC circuit meets the binary weight relationship, and the conversion result reaches 12-bit conversion accuracy. In addition, the voltage reference circuit module is successfully used to make the ADC work in two working modes: sleep/wake-up, and the power consumption of the circuit is greatly reduced. When tested at a clock frequency of 2MHz, the power consumption of the SAR ADC is less than 1mW. The results show that the SAR ADC circuit based on the touch screen controller designed in this paper has low power consumption and high precision. It can be used in any medium-precision and medium-conversion rate occasions, and has a good guiding role in the optimization design of the touch screen controller.