Application design of PAD in dynamic reconfigurable receiver structure

Reconfigurable structure is a computing technology that can reorganize its own resources according to specific computing conditions, realize self-optimization and self-generation of hardware structure. Dynamic reconfigurable technology can quickly realize the logical reconstruction of the device. Its emergence provides a solution that combines the flexibility of general-purpose processors and the high speed of ASIC circuits for dealing with large-scale computing problems. In the system design that the author is engaged in, when some performance of analog devices changes but cannot be updated and adjusted in time for the back-end digital baseband processing, such as the influence of the temperature drift characteristics of the filter caused by too long working time, at this time, programmable analog devices can be used to replace part of the front-end fixed analog devices, and then the FPGA module can be dynamically reconfigured in real time, and finally the system performance can be optimized.

Programmable Analog Devices

Programmable analog devices are a new type of integrated circuit that has emerged in recent years. They belong to analog integrated circuits, that is, the input, output and even internal state of the circuit are analog signals that change continuously over time and whose amplitudes are not quantized; at the same time, this type of device is field programmable, that is, the user can obtain the required circuit function by changing the configuration of the device. To support the above programmable capabilities, programmable analog devices need to be based on programmable analog blocks (CABs) and programmable interconnect networks (PINs), and are composed of configuration data storage, input units, output units or input and output units [1] (see Figure 1).

Figure 1: Programmable analog device block diagram

Most programmable analog devices operate under a single +5V power supply voltage, with a rated power consumption of 100mW. Due to special measures, their input and output linear ranges can usually reach close to the full power supply voltage range; the closed-loop bandwidth has reached hundreds of kilohertz to tens of megahertz; and indicators such as frequency distortion, common-mode rejection ratio, and internal noise have also reached the level of medium and high-precision operational amplifiers.

Although the accuracy of analog signal processing is lower than that of digital signal processing, it can still meet the requirements of many important applications for calculation accuracy, and the required circuit scale is smaller and the cost is lower. At the same time, its programmable characteristics can also achieve accurate automatic tuning and automatic gain control, significantly improving the anti-interference ability of the communication system.

Phase Detector Implementation

TRAC (fully reconfigurable analog circuit) is the general name for a series of field programmable analog devices from the British company FAS. It provides a way to solve various common signal processing problems starting from signal processing problems. The device refers to the arithmetic unit of an analog computer and expands it, so that each programmable analog unit inside the device has eight arithmetic functions such as addition, subtraction, negation, logarithm, antilogarithm, integration, and differentiation. Therefore, it is very convenient to complete the design of the relevant unit by simply selecting the type of operation and giving the necessary parameters, without having to consider the specific details such as the internal structure of the unit circuit. The internal units are connected in a fixed manner from left to right, and the input and output terminals of all units are led out to the device pins. It is also allowed to modify this basic connection by using the "through" and "shutdown" functions of each unit or by using an external "short-circuit" [1] (see Figure 2).

Figure 2 Schematic diagram of TRAC device structure

In the cognitive radio hardware platform design that the author is engaged in, since it is necessary to identify and extract weak signals from a strong signal background environment, the TRAC device can be used to form a phase-sensitive detector and use it as part of the latch amplifier. To achieve this goal, the circuit needs to work like a narrowband filter, removing most of the unwanted strong signals and allowing only the weak signal to be measured to pass.

Figure 3 shows the basic block diagram of a phase detector. The input signal and the reference switching signal have the same frequency and phase. A full-wave rectified signal is expected from the switching output shown, and after passing through a low-pass filter, a DC voltage output proportional to the AC signal potential can be obtained. In practical applications, the input signal may be very small, so a preamplifier stage is required to support accurate detection. This is because it is usually necessary to continuously change the frequency of the reference signal within a certain range while measuring the corresponding DC output. Similarly, if a single frequency needs to be detected, the reference signal must have the same frequency as the input signal to be measured. Since the phase detector is also sensitive to phase, the maximum output voltage is obtained when the two signals are in phase.

Figure 3 Phase detector block diagram

The phase detector and low-pass filter need to be realized by two TRAC devices. External components are essential for both the amplifier and the filter, so the components that meet the conditions must be reasonably selected.

Implementation of Programmable ADC

Cognitive radio receivers have high requirements for high-performance analog-to-digital converters (ADCs) and analog devices used in their front-ends, while FPGAs urgently need to be dynamically reconfigurable in baseband digital signal processing. In order to meet the above requirements, we can first consider using programmable analog devices to implement ADCs. The following are two specific implementation methods.

FIPSOC Mixed-Signal System-on-Chip

SIDSA's FIPSOC mixed-signal system-on-chip is an ideal tool for rapid development of analog and digital integrated applications. The FIPSOC chip includes an embedded enhanced 8051 microprocessor, a field programmable gate array (FPGA), and a group of flexibly configurable analog units for signal conditioning and data acquisition applications. Compared with separate analog and digital FPGA solutions, the use of the FIPSOC mixed-signal system-on-chip can shorten the product design cycle by 30-40%.

The single-chip system of programmable analog and digital units and 8051 includes analog units, conversion units, programmable digital units, 8051 core and all devices in this series have compatible memory layout. The conversion unit contains 4 DACs (resolution can be configured to 8 to 10 bits). Using the successive approximation algorithm, these DACs can be used to implement an ADC with a sampling rate of up to 800KHz (see Figure 4).

Figure 4 Block diagram of data conversion module

The data conversion module contains four 8-bit successive approximation registers (SAR), which can work in conjunction with the internal DAC to obtain analog/digital conversion.

Each channel has an independent SAR, which receives the result of successive comparison and drives the corresponding DAC. The conversion of each channel can be performed independently. When the conversion module is programmed for 9- or 10-bit ADC conversion, the corresponding SAR forms a group: for 9-bit ADC, SAR1 and SAR2 are a group, SAR3 and SAR4 are a group; for 10-bit ADC, all 4 SARs form a group. At this time, the grouped SARs work for 1 to 2 cycles each. At the end of the conversion, the SAR stores its content in the input/output register and enables the interrupt generation module. In the continuous conversion mode, the next conversion will be started. During the conversion process, the programmable logic module can independently issue conversion commands, which will cause errors in this and the next conversion. In the continuous conversion mode, this will cause a fatal error because the error can be transmitted and will result in unpredictable results.

The control part is a standard 8051 microprocessor. After compounding, the 8051 core first configures the programmable cells, and after configuration, it can be used as a general microprocessor. In order to better support the dynamic reconfiguration characteristics of FIPSOC, some improvements have been made to its instructions and functional units.

Cypress PSoC Devices

Cypress Semiconductor's PSoC mixed-signal architecture perfectly integrates programmable analog and digital blocks with 8-bit microcontrollers. This unique combination of features enables designers to achieve unparalleled flexibility for a variety of applications. The latest CY8C23x33 device uses an 8-bit successive approximation ADC to achieve a sampling rate of up to 375Ksps. In addition, the solution also has 26 GPIOs for excellent configurability, which can quickly adapt to changing feature requirements. The device uses a 5x5mm QFN package to minimize board space.

PSoC devices integrate configurable analog and digital circuits controlled by an on-chip microcontroller, providing more powerful design modification capabilities and further reducing component count. PSoC devices include up to 32Kb of flash memory, 2Kb of SRAM, an 8x8 multiplier with a 32-bit accumulator, power and sleep monitoring circuits, and hardware I2C communication [2].

All PSoC devices are dynamically reconfigurable, allowing designers to change the form of internal resources at will during operation and use fewer components to complete a given task. Easy-to-use development tools allow designers to select configurable library elements to provide analog functions (such as amplifiers, ADCs, DACs, filters, and comparators), as well as digital functions (such as timers, counters, PWMs, SPIs, and UARTs). The analog performance of the PSoC series devices includes rail-to-rail inputs, programmable gain amplifiers, and ADCs with resolutions up to 14 bits, as well as ultra-low noise, input leakage current, and voltage offsets.

A single PSoC device can integrate up to 100 peripheral components, saving customers design time, reducing board space and power consumption, and lowering system costs while improving system quality.

Receiver Design

Based on the results of the above analysis and combined with the front-end hardware circuit, a receiver structure is specially designed to realize certain cognitive radio functions (see Figure 5).

Figure 5 Receiver structure

The front-end low-noise amplifier is ADA4857-1, which is an ultra-low-loss, low-power, high-speed operational amplifier. Its 3dB bandwidth in SOIC structure can reach 750MHz, and its open-loop gain is 57dB, which basically meets the requirements of this receiver for the front-end low-noise amplifier. When building the circuit, special attention should be paid to the influence of power supply bypass, parasitic capacitance and peripheral device selection on the full performance of the amplifier [3].

The DDS (direct frequency synthesizer) uses the 1GSPS AD9858, which uses advanced DDS technology and a built-in high-speed, high-performance D/A converter to form a digitally programmable, fully high-frequency synthesizer. It can generate an analog output sine wave up to 400MHz, which fully meets the receiver's requirements for the local oscillator.

Mixers, bandpass filters, amplifiers and anti-aliasing filters can all be uniformly implemented by Cypress's PSOC device cy8c23x33. The PSOC analog system includes an 8-bit SAR ADC and 4 configurable modules. Each analog module consists of an operational amplifier circuit, allowing the establishment of analog complex signal flows. At the same time, analog peripheral components are very easy to customize to meet the needs of special applications. PSOC can implement a programmable bandpass filter and a low-pass filter to replace the bandpass filter and anti-aliasing filter required by the receiver front end, implement an instrument amplifier with an optional gain of up to 93dB to replace the intermediate frequency amplifier, and a multiply-add accumulator provides a fast 8-bit multiplier to replace the mixer. The above programmable analog devices can basically meet the performance requirements of the receiver front end. We use the PSOC designer to configure the PSOC work, write applications using the PSOC and debug the applications. Take the amplifier as an example. First, find this module in the designer and create a new circuit, set up the peripheral circuit components, set the initial values ​​according to several parameters such as setup time, conversion rate and gain bandwidth, generate application code, and then write the main program and any subroutines of the subsystem. If all the programs are correct, a HEX file will be generated and finally executed by the debugger in the PSOC designer. It downloads the HEX file to the in-circuit simulator (ICE). At this point, a programmable amplifier is set up and can be put into use.

The programmable ADC could have been implemented by Cypress PSOC, but the ADC sampling rate implemented by PSOC is only 375 Ksps at most, which cannot meet the bandwidth requirements of the cognitive radio receiver front end. Therefore, it is possible to consider using the FIPSOC device of SIDSA. At the same time, the back-end baseband digital processing task can also be implemented by the 8051 core and FPGA in FIPSOC. The integrated development tool running in the WINDOW environment is used to design and program the ADC. Combined with the above content, when designing the ADC, it is necessary to first set the initialization values ​​of the external input/output pins, internal input/output pins and internal signals, and then configure the mP control register and static RAM to achieve the required performance requirements. The digital macro cell (DMC) is a programmable digital unit of the FPGA. It is a programmable unit based on the lookup table structure. It has combinational logic and sequential logic resources, and the combinational part and the sequential part are connected by wiring resources. Using the dynamic reconfiguration mode, multiple DMC units can be set, the hardware circuit can be changed, and then the front-end programmable analog devices can be updated in real time to a certain extent. This technology is currently under exploration and research [4].

The above is only the separate design of each module, but to design the entire receiver system, it is also necessary to pay enough attention to the connection between each module and the reference clock and many other aspects. Each module has its own input/output port. In order to achieve the predetermined system performance requirements, it is necessary to strictly refer to the technical manual and its own pre-wiring arrangement to connect each input/output port. As for the clock, avoiding the use of gate circuits with large clock jitter is one of the principles that need to be strictly followed in circuit design. Only on this basis can the performance of the device be maximized; in addition, taking FIPSOC as an example, except under certain conditions, the relative phase of the 8051 clock and its replica clock sent to the DMC will be exchanged, and the clock stop does not affect the clock synchronization; each time the different clocks are reconfigured, they must be resynchronized.

Conclusion

At present, the feasibility of the above receiver structure design has been theoretically proven. The next step will be to gradually build a specific hardware platform and test and verify it. In addition to programmable analog devices, the emerging evolvable hardware (EHW) research field aims at hardware online adaptation and also uses programmable analog devices as an important evaluation method and implementation carrier for realizing automatic design and online adaptation of analog circuits. It can be expected that with the continuous advancement of analog programmable technology and the gradual enrichment of device varieties, programmable analog devices will become the preferred device and the best choice for realizing analog circuits.