Implementation of industrial control system based on ATOM processor

The ATOM processor uses a groundbreaking 45-nanometer process to integrate 47 million transistors into a single chip with an area of ​​less than 25 mm2, making it the smallest and lowest-power X86 processor in Intel's history. Due to its excellent performance and low power consumption, the ATOM processor is very suitable for mobile Internet devices, low-power mobile Internet computers, basic Internet desktops, and industrial applications with stringent power requirements [1].
This paper proposes a complete industrial control system design solution based on the application requirements of small size and low power consumption of industrial control systems and the characteristics of Intel's latest low-power mobile ATOM processor.
1 Platform Architecture
The "Centrino Atom Processor Technology" platform defined by Intel includes Intel Atom processors (Silverthorne and Diamondville), low-power "companion chips" (bridge chips), and ultra-thin and ultra-light designs. Diamondville and the 945GSE bridge chip form the Navy Pier platform. Silverthrone and the bridge chip code-named Pouslbo form the Menlow platform. The Navy Pier platform uses two bridge chips, which are relatively large and are mainly suitable for consumer electronics products. The Menlow platform uses an integrated bridge chip. The entire platform is small in size and has very low power consumption, making it very suitable for industrial platform applications. This article uses the implementation solution of the Menlow platform.
The Menlow platform is mainly composed of the Poulsbo bridge chip and the ATOM Z5×× processor. The Poulsbo bridge chip has an area of ​​22 mm×22 mm and can provide two PCI-E x1 slots, one IDE PATA 100 interface, three SDIO and MCC memory card slots. It integrates many modules such as USB 2.0 controller, memory controller, high-definition audio controller, and graphics core. The graphics core uses the GMA500 core with a core frequency of up to 200 MHz. It supports DirectX 9, OpenGL and 3.0+Shaders, and also supports hardware decoding of H.264, MPEG2, MPEG4, WMV9, etc. [2].
This design uses a single-channel memory controller that can support DDR2 533 and DDR2-400. The bridge chip expands the Ethernet port, LVDS, DVO port, 4 USB ports, 1 PATA and SATA. The audio is HD Audio. Other functions such as RS232, system light indication, and power on/off control are implemented through LPC bus expansion. The system block diagram [5] is shown in Figure 1.

2 System power design
Power supply is an important part of ATOM system design. The difficulty lies in: (1) Because it is necessary to power multiple functional modules, many switching power supplies are required, which has a great impact on the EMI electromagnetic interference of the entire system. (2) The power conversion efficiency must be fully considered. ATOM processors are mainly used in portable applications. When selecting devices, not only must the power be sufficient, but also economical and efficient. The battery power supply time is also an important part of the overall system performance assessment. The heat generated by power loss during power conversion will also cause the system temperature to rise, resulting in an increase in the system cooling cost.
In this design, LT4100 is used to implement battery charge and discharge management. VIN_3.3 V is the standby voltage. As long as the external power supply or internal battery has power, the chip 7803 will work. This chip is mainly responsible for powering the EC. Once the EC detects the power button signal, it generates a power pulse POWEREQ#, the LT3780 starts working, the power management circuit starts running, and the subsequent circuits are enabled in sequence. The SC454 is selected as the CPU core power supply chip in the design. This chip is a single-phase high-performance PWM controller dedicated to the enhanced IMVP-6 and IMVP6+TM processors. The chip supports all IMVP-6/6+ requirements, such as effective voltage stepping, dynamically adjustable output voltage, deep sleep settings, etc. SC454 uses hysteresis control technology, which has a faster response speed than traditional PWM controllers. The sensitive resistor is removed, the power consumption is reduced, and the PCB layout is simplified. The integrated intelligent drive technology controls the MOS tubes on the upper and lower sides through soft switching, effectively reducing overshoot, ringing and EMI. The chip provides the system clock enable pin CLKEN# and the overheating indication signal VRTT#. After the power output is stable, CLKEN# turns on the system clock chip; when overheating, VRTT# provides a signal to the bridge chip to shut down the system. SC454 adjusts the core voltage according to the processor load. When the load increases, the voltage is gradually reduced, so that the CPU power consumption under high load can be reduced. This ensures that the system has a relatively low TDP, average and active power consumption.
SC486 is used to generate the 1.8 V power supply for DDR memory, SC415 generates the core voltage +VCCP and auxiliary I/O voltage +V1.5S of the bridge chip, and SC454 generates +VCC_CORE. In actual application, the power-on sequence is very important. Generally, SC486 is turned on first, and after the output voltage is stable, SC415 is turned on. After +VCCP and +V 1.5S are stable, SC454 is enabled to output +VCC_CORE. The shutdown sequence is the opposite. This project uses CPLD to realize the power on/off and low power consumption processing of the power supply, including the shutdown, standby, sleep and restart functions after entering the operating system. As shown in Figure 2.

In order to improve the reliability and electromagnetic compatibility of the system, the reasonable layout of the power supply is very important. The correct solution is to divide the corresponding number of power blocks in the power layer of the printed circuit board according to the power layout. Each power block should ensure sufficient area to load the working current, and have its own independent return ground line to effectively avoid interference between different power supplies. Secondly, decoupling capacitors with different frequency response bands should be added to the power supply to keep the power supply pure.
3 Clock topology
The various clock signals required by the system are generated by the clock generator ICS9UMS9001, which has the following features: a clock chip designed for ultra-mobile PCs (UMPCs), which minimizes EMI electromagnetic interference inside the chip; an external 14.318 MHz crystal oscillator is used as the oscillation source; it supports power management mode, with two modes: low power consumption and normal operation. In this design, the mode selection input pin is connected to the CLKEN# of SC454 to ensure that the clock generator works when the CPU core is powered on, and enters the low power consumption mode synchronously in sleep, standby, etc.
4 System audio
Pouslbo integrates an HD Audio digital audio controller. Compared with the traditional AC'97, HD Audio has the characteristics of wide data transmission bandwidth, high audio playback accuracy, support for multi-channel array microphone audio input, lower CPU usage and universal underlying driver. In this design, a CODEC chip ALC888 that complies with the HD Audio specification is externally expanded to realize universal audio functions, and the audio amplifier uses SM2303[5]. ALC888 is a 7.1+2 channel HD Audio codec chip with 2 stereo input ADCs and 10 DAC outputs. It can almost support 7.1 audio loopback and 2 stereo outputs at the same time. The chip has 2 SENSE signal lines with insertion sensing function, which can sense the insertion and removal of audio plugs. Pouslbo's HD Audio digital audio controller communicates with ALC888 through a dedicated "Azalia Link" bus. The specific signal lines are bit clock (Bit Clock), serial data output (Serial DatOut), serial data input (Serial Data In), synchronization signal (Sync) and reset signal (Reset#). The bit clock frequency is 24 MHz and is generated by Pouslbo, as shown in Figure 3.

To ensure good audio quality, analog signals and loops must be isolated from digital circuits during PCB layout. The analog part of the audio circuit is very sensitive to digital noise. The best way to prevent noise is to follow the principle of "functional partitioning" and establish an independent analog signal area to completely isolate all components, signal paths, power layers, and ground layers of the analog and digital parts. This area is usually placed at the edge of the board to shorten the signal line as much as possible and reduce the possibility of interference to the audio signal line. The ALC888 has a clear analog-to-digital division and no crossover area, which makes board layout very convenient [4].
5 System Video LVDS, DVO
Pouslbo has an integrated GMA 500 and is equipped with hardware decoding support. It can support MPEG-4 AVC (H.264) and can play VC1 (WMV9), MPEG-2, and MPEG-4 videos without adding extra load to the CPU. Pouslbo has an integrated LVDS and SDVO interface that can be directly connected. In this design, the LCD screen uses Philips' LP121×04, which is 12.1 inches, 1024×768 pixels, and has an LVDS interface, which is very convenient to use. According to the needs of actual applications, a DVO interface is expanded.
6 External Interfaces
The network control chip uses Realtek's 64Pin LQFP package RTL8111, which is based on the PCI-Express interface and truly solves the problem of insufficient bandwidth of the current standard PCI interface for Gigabit network cards. It integrates a 10/100/1000 converter, supports remote wake-up and network wake-up, is compatible with 802.3 series protocols, and supports PCIE 1.1 protocols. The chip is embedded with a PCIE physical layer with an adaptive equalizer, and the PCB wiring length can reach 40 inches, which is very convenient to design and use.
Pouslbo only supports PATA ports. In this design, JM20330 is used to implement SATA/PATA conversion. This chip contains the physical layer, connection layer, transport layer of serial ATA and the controller (application layer) of parallel ATA. It complies with the protocol of serial ATA1.0a and supports a data rate of 1.5 GHz. The master and slave modes can be set by jumpers and support PIO mode and UDMA mode [5].
Pouslbo has an internal integrated USB interface, which is directly led out to the port through a filter. In this design, four USB external interfaces are led out, as shown in Figure 4.

7 LPC bus
Pouslbo integrates an LPC bus controller. LPC bus is a new specification developed by Intel to cancel the slow ISA [3]. Hardware that used to run on ISA, such as keyboard, mouse, serial port, parallel port and other slow peripherals, can be controlled by SUPER IO chips that support LPC, and are fully compatible in software. In this design, the selected LPC external embedded chip is IT8513, which is mainly responsible for external keyboard, battery power, system indicator light, power on and off operation, and realizes level conversion through ADM3202, and extends two serial ports. The system BIOS chip is also mounted on the LPC bus. After power-on, the bridge chip provides the clock, reads the BIOS firmware content, and guides the system to start.
The system BIOS uses the Phoenix BIOS 6.0 source code software package, and secondary development is carried out on this basis. BIOS can be divided into four major modules according to its function: power on self-test POST (Power On Self Test), basic interrupt service routines, system BIOS settings and boot loading. POST provides a series of diagnostic routines to test system components, initialize data areas and report system information [6]. Generally speaking, after the POST test passes, it can basically ensure the normal operation of various hardware devices, thereby allowing the system to operate normally, as shown in Figure 5.

For low-power platforms, performance is no longer the only criterion, or even the most important criterion, but low power consumption and low heat generation are the biggest highlights. This system not only completed all debugging and testing without a heat sink, but also maintained a very low temperature. The average power consumption of the measured system board when it was with a solid-state hard drive and no screen connected and running the Windows XP operating system was 5.96 W, and the standby was 5.6 W. When tested with a screen, the average power consumption was 9.39 W, and the standby was 6.39 W. The common 2.8 Ah 3-cell lithium-ion battery on the market can last for more than 4 hours under normal use. The whole machine is small in size, with an actual size of 10 cm×6 cm.
In the whole machine test, the system can run 3DMark and other test software continuously and stably on the Windows XP operating platform for more than 24 hours, which can fully meet specific low-power industrial uses. This system has been successfully applied to the customer's portable mobile computer system and has passed the high and low temperature, rain, vibration, drop and impact tests organized by the military, and the stability meets the requirements. The performance has also reached the level of similar commercial platforms. Table 1 shows the test data at room temperature using EVEREST v5.50.2100 software. Compared with a commercial platform of a professional company in Taiwan, the test data of this motherboard in terms of floating-point operations, CPU performance, memory read and write are comparable, and have reached the original design requirements of various performance indicators.
References
[1] Intel Centrino AtomTM Processor Technology Design Guide. March 2009, Revision 2.1.
[2] External Design Specification (EDS) System Controller Hub (Intel SCH) Small Form Factor. February 2009, Revision 2.1.
[3] Intel Low Pin Count (LPC) Interface Specification, August 2002, Revision 1.1.
[4] Intel Atom ^TM Processor and Intel System Controller Hub US15W Layout Checklist , June 2008 Revision 2.1.
[5] Menlow Platform Crown Beach Customer Enabling Board Schematics. November 2007, Revision 1.5.
[6] Han Shanxiu. Design and Implementation of BIOS [J]. Microelectronics and Computers, 2005, 22(11): 1132, 115.