Design of Multi-channel Digital I/O Based on STD Bus

In the field of industrial control, digital I/O has been widely used for its simplicity and flexibility. In the past, the application and increase of digital I/O were usually achieved by using GAL and special I/O chips with decoding expansion. Although this method can meet the requirements to a certain extent, it is difficult to apply a larger number of I/O applications, such as dozens or even hundreds of digital I/Os. In order to meet this requirement and further improve the efficiency of digital I/O, a design based on the STD bus was specially designed for multi-channel digital I/O. The CPLD of Xilinx was used for programming and development, realizing 64-bit digital input DIN 0~DIN 31 and 64-bit digital output DOUT O~DOUT 31. At the same time, each I/O can be independently programmed and can be used as both input and output.

1 STD bus

At present, the STD standard bus has become one of the most popular standard buses in the field of industrial control, mainly used in 8-bit microprocessor and single-chip industrial control systems. The typical structure of the STD bus is shown in Figure 1.

In the actual application of industrial control systems, the host computer, main control module, etc. often need to access other single-chip computer systems through the STD bus according to the protocol and characteristics of the STD bus. For example, in a certain measuring device, the host computer and the main control module can collect the sensor values ​​through the I/O module and A/D module interface on the bus, access the RAM module through the STD bus, and communicate and exchange data between the main control module and other controllers on the bus, and between the main control module and the host computer through the STD bus, forming a micro industrial control network. The multi-channel digital I/O in this article is a module in the STD bus.

2 Hardware design of multi-channel digital I/O

2.1 Circuit composition

It is mainly composed of programmable logic circuit, level conditioning circuit, bus interface circuit and power supply circuit. The programmable logic hardware adopts Xilinx's CPLD device XC95288, and uses Xilinx's Project Navigator (ISE) integrated development environment for programming and development; the level conditioning circuit adopts 74LS245, which has the function of input and output level conversion, and can also interface with peripherals through relays or photoelectric isolators; the bus interface circuit adopts 74LS245, and reads and writes the DIR (direction) of 74LS245 to realize data communication with the STD bus. The power supply circuit provides the necessary power supply system for CPLD and level conversion circuit.

The hardware implementation block diagram is shown in Figure 2. The dotted box is the hardware circuit part of the multi-channel digital I/O.

2.2 Performance characteristics

The XC95288 CPLD chip has 208 pins, of which 168 are user I/O pins. In addition to the 40 I/Os occupied by the address bus, data bus, and chip select signals, the remaining 128 I/Os can be used as general I/O programming.

Small area Such a large number of I/Os are completely implemented by a CPLD, which simplifies the circuit design process, reduces the design area of ​​PCB, and improves the stability of digital I/O;

High flexibility Since each I/O can be independently programmed, it becomes very flexible during use and its input and output can be changed at any time according to on-site needs, providing great flexibility for product enhancement and upgrading in the field of industrial control applications.

In addition, the design also has the characteristics of high transmission speed (determined by the transmission characteristics of CPLD) and good level compatibility, which can meet the various needs of users in testing, control and design applications.

The system uses the industry-leading FPGA design environment Xilinx ISE, which combines advanced technology with a flexible and easy-to-use graphical interface to achieve the best hardware design in the shortest time. The XC95288 CPLD is a low-power 3.3 V device with 288 macro cells, 6,400 available logic gates, and 168 user I/Os. Coupled with the flexible and highly optimized VHDL hardware description language, it realizes the programmatic design of 128-bit digital I/O.

3.1 Partial Program Code

Part of the program code is as follows


: where addr is the 10-bit address bus; bd is the 8-bit data bus; en_245 and dir_245 are the chip select enable and direction signals of the STD bus interface chip 74LS245 respectively; tempx is an on-chip register; io_inx and outx are 8-bit input and 8-bit output I/O ports respectively.

3.2 Performance Description

The selection of multiple digital I/O ports is determined by a 10-bit address, and different addresses operate differently. For the I/O port, when the I/O is not dynamic, the data bus is in a high-impedance state, which avoids bus conflicts, improves the stability of the I/O port, and reduces unnecessary errors caused by high-speed data transmission conditions. According to the needs of the I/O input and output on site, the program can be modified to flexibly change the function of the port. In addition, for the output port, a function of reading back the data after writing is added, so that the host computer can verify the correctness of the written data at any time. For peripheral signals, level matching is achieved through the signal conditioning board, which further increases the functional reliability of this design.

4 Conclusion

With CPLD device as the core, Xilinx's ISE is selected as the hardware development platform, and VHDL programming language is used, which fully utilizes the characteristics of programmable logic devices and gives play to the programming advantages of VHDL hardware description language. The number of chips is reduced, which not only achieves system miniaturization but also reduces costs. The program has passed comprehensive experiments, applied the communication characteristics of the STD bus, and is also very convenient to communicate with other boards and devices on the bus. It not only solves the general problems of industrial communication networks, but also meets the higher requirements of industrial general I/O. In short, this multi-channel digital I/O design has high capacity, low power consumption and high speed. It is not only universal and practical, but also flexible and portable, easy to debug, and provides a good attempt for high-speed I/O development and design. I believe it will have broad application prospects in many industries.