Design of LED based video display board design

It is estimated that tens of thousands of large LED video display panels have been installed worldwide. As the overall system price drops and the operation of the display panel is simplified, LED video display panels will become more popular. This article introduces a basic low-cost LED video display module. This new design uses an inexpensive FPGA chip to complete the distribution of the digital video bit stream and the MAX6974 LED driver to form a QVGA (320×240) resolution LED video display. The display panel can be controlled by a PC and used as a secondary monitor to display any text, graphics, or multimedia information.

1 Current LED display card architecture

Currently, all top LED video display board manufacturers use LED video screens with different color pixel sizes but similar structures. The video display module has a pixel range of about 256 to 15,552. The video display modules can be spliced ​​together to form a video wall with a side length of several meters. Each video display module has a different PCB on which the LEDs and their drivers are installed. In addition, the PCB on which the LED drivers are installed also has an FPGA and video cache chip installed. In a video wall, the video display modules are usually connected by coaxial cables. The video wall is connected to the control and video processing unit via optical fiber. The control unit is used to configure these video display modules and correctly select the video source. The video processor receives the selected video signal, converts the format and sends the correct data information to the corresponding pixel location. The video processor also needs to perform data caching and proportional adjustment. The controller and video processor unit for this application are professional equipment and are very expensive.

1.1 Maxim Solution

The unique features of the MAX6974 LED driver can be combined with a low-cost, medium-sized FPGA to build an LED video display board, with the entire system controlled by a PC, as shown in Figure 1. An additional video interface PC card can support different video signal sources to form a complete LED video display board with few electronic components and no specialized equipment.

1.2 MAX6974 LED Driver Characteristics

The MAX6974 LED driver is designed for LED video display board applications. Each LED driver contains 24 equal constant-current, PWM LED driver ports that can drive 8 or 16 (dual-mode) RGB pixels. To accommodate video or static images and eliminate black screens, the chip's PWM rate is very high. When the video refresh rate is 60 f/s (frames per second), the PWM rate is approximately 7 680 Hz. The MAX6974's data input interface consists of an LVDS clock and a pair of LVDS data. It is also possible to connect MAX6974 LED drivers in series through the data output interface to provide higher data bits, which also contains LVDS clock and LVDS data pairs. Depending on the video refresh rate and clock frequency, hundreds of MAX6974 devices can be connected together through the LVDS interface. Using this interface, the LED driver and video display module PCB can be connected together through a few feet of twisted pair cable.

The MAX6974 can control the brightness of each LED in three ways. First, each individual LED (red, green, or blue) has a 12-bit PWM brightness controller, which is much higher than the 8-bit resolution per color specified by the DVITM interface. The remaining bits can be used for contrast adjustment to adapt to different ambient light conditions. Second, the 7-bit PDM brightness control is used to adjust all LED driver ports. These PDM bits can be used for brightness control. Finally, each group of LED driver ports has a constant current control (6 mA to 30 mA) with a step size of 256. These calibration steps are used to configure the required video color at different temperatures.

1.3 MAX6974-based LED video display board architecture

The LED video display board uses an FPGA to implement the distribution of video data bits. It can also capture control frames and forward them directly to the corresponding registers inside each MAX6974 LED driver. Figure 2 shows the reference design block diagram of QVGA resolution (320×240), which uses a TFP401A DVI receiver, an AT24C02 EEPROM for storing EDID, an EP2C20 FPGA, and 9,600 MAX6974 LED drivers to drive 76,800 OVSRRGBCC3 RGB LEDs.

The DVI signal on the left side of the block diagram is received by the TFP401A DVI receiver, and the AT24C02 EEPROM provides EDID to the Windows? operating system. The deserialized signal and TMDS decoded signal are sent to the EP2C20. The video bits are re-arranged and transmitted to the LED video module PCB column through 5 LVDS channels at a speed of 32 Mb/s. Each LVDS contains 2 differential pairs, CLKI(O)±, DIN(OUT)±, 1 LOADI(O) pin and 1 GND (ground) pin, for a total of 6 lines. Each LED display module PCB contains 64 MAX6974 LED drivers and 512 OVSRRGBCC3 RGB LEDs.

1.4 Video stream allocation and video frame control

The lowest resolution of DVI is VGA. This QVGA reference design can be used for odd or even pixels with interlaced scanning. The half-pixel clock rate of the TFP401A DVI receiver is 12.5 MHz, and the blanking period occupies about 40%. Since the MAX6974 interface is only used for odd or even lines, there is no need to consider the blanking period. The serial conversion (24-bit RGB) QVGA data rate is 12.5/2/1.4×24=107.14285 Mb/s. Considering the 8-bit resolution of DVI per color, corresponding to the 12-bit converter of the MAX6974 per color, the effective data rate is (107.142857/8)×12=160.714286 Mb/s. The FPGA buffers the pixel data stream from the TFP401A DVI receiver, divides the data stream into 5 groups, and then sends it to the corresponding LVDS channels. The data rate of each LVDS channel is 160.714286/5 = 32.1428571 Mb/s.

Each pixel received by the TFP401A DVI is transmitted sequentially from left to right per line and from top to bottom per frame. Each PWM frame format of the MAX6974 requires the same color information to be transmitted in groups of 8 pixels, as shown in Table 1. A buffer is required to store at least 8 pixel data to support this format conversion. Considering interlaced scanning and blanking, in order to maintain a fixed transmission rate of the LVDS channel, the reference design uses a buffer to store a frame of video data. The buffer can connect multiple MAX6974 devices at both ends of the PCB to avoid using a long LVDS link from right to left.

In addition to transmitting the PWM information of each port, three data frames with the frame header CMD bits of 010101, 101010, and 111111 transmit CALDAC, global brightness PDM, and configuration information through the MAX6974 LVDS interface, as shown in Table 2. Each frame header contains 24 bits, the first byte is the synchronization template 11101000, followed by 6 bits of CMD and 10 bits of counter value (CNTR). The CMD bit of each port PWM data frame is 000000.

In addition to PWM information, data frames are also sent through the DVI interface using a PC-based GUI. The data frame type is identified by the corresponding circuit inside the FPGA. In a control video frame, each pixel from line 0 to line 1 contains 24-bit frame header configuration information (HDR); lines 32 and 33 contain frame header information for global brightness PDM, and lines 64 and 65 contain frame header information for CALDAC. In this reference design, the 30 lines of data after each group of 2 lines of frame headers correspond to the 30 lines of information on the LED display module PCB. Each specific LVDS column provides information for 64 pixels per row, which is used to transmit information for 64 MAX6974 LED drivers on each LED display module PCB. Each pixel of each MAX6974 device includes 24 bits of control information, and data above 95 lines are not used in video frame control.

1.5 Video Display Board Control GUI

The GUI shown in Figure 3 is used to configure the global brightness PDM and CALDAC registers of all MAX6974s in the reference design. The GUI includes a global setup option for adjusting the relevant parameters of all chips in the video display board, and also contains a device tab for adjusting the parameters of each chip. The settings of all registers and MAX6974 LED drivers can be stored in a file and downloaded when the video display board is running. An initialization setup file is provided, which includes the initial settings of typical register parameters, greatly simplifying the initialization process of the video display board.

The GUI appears as a separate operating window on the Windows operating system. Once the Write button on the GUI is enabled, it creates a video control frame and sends it to the video display board. The video control frame can only be displayed at a video refresh rate of 60 Hz. The video control frame also occupies the entire screen of the video display board; however, the FPGA detects the control frame header line and sends the corresponding information to the MAX6974 registers. Therefore, the content of the video control frame is not displayed on the video display board. Although the control information is also transmitted when the video frame is refreshed, the human eye will not notice these updates.

2. Implementation

The DVI receiver board includes the TFP401 DVI receiver and the AT24C02 EEPROM, along with a few bypass capacitors. The TFP401 DVI receiver performs serial-to-parallel conversion and TMDS decoding, and guarantees that both odd and even pixels of the RGB bits are obtained at half-pixel clock rate. Because the minimum resolution of the screen determined by DVI is VGA, the reference design eliminates each adjacent pixel to support interlaced scanning. The half-pixel clock is very convenient for the FPGA, allowing it to select the required pixels. Before the Windows operating system recognizes the display, the display is detected by the DDC according to the I2C protocol. The display then responds with its EDID, which contains manufacturer information and operating information. Similarly, the AT24C02 EEPROM is used to store the EDID information of the LED video display board. The manufacturer ID must be obtained from the Video Electronics Standards Association (VESA). In this reference design, the EDID of the DVI LCD display is borrowed and stored in the AT24C02 EEPROM. When all three address pins are grounded, the I2C address of the AT24C02 EEPROM is 0x0A, which is the address that the operating system will search.

The FPGA board mainly includes 2 SRAMs and 1 Altera?誖FPGA device. The FPGA has LVDS interface and memory reading function. In this reference design, FPGA is mainly used for output distribution of DVI digital video information. Another important function of FPGA is to identify data frame configuration, global brightness PDM and CALDAC information. When the video control frame is identified, all the data frames except the independent PWM information are received and sent directly to the corresponding MAX6974 registers.

Figure 4 shows the internal functional circuit of the FPGA. The data bits of a frame of pixels are stored in the SRAM buffer. The line buffer inside the FPGA is used to connect the TFP401A DVI receiver and the LVDS channel. Two line buffers, one for receiving the data bits received by the TFP401A, and the other line buffer connected to the SRAM is used to receive the data from the TFP401A DVI receiver. Similarly, two line buffers are used for each LVDS channel. The FPGA provides a complete logic circuit to keep the DVI and LVDS data throughput consistent and provide the required timing of the SRAM data, address, and control signals. Because the SRAM is a single port, the memory access needs to be configured inside the FPGA when performing read and write operations at the same time.

Each MAX6974 drives 8 RGB LEDs. Each display module contains 64 MAX6974 LED drivers, distributed in 8 rows and 8 columns, and 512 RGB LEDs in 8 rows and 64 columns. All LEDs are mounted on one side of the PCB, with an LED center distance of 8 mm (top, bottom, left, and right spacing). The display module circuit board size is 512 mm×64 mm. All MAX6974 devices are mounted on the other side of the PCB. On the side where the MAX6974 devices are mounted, power and ground wires are laid, including 1×6 connectors. A total of 2 sets of 1×6 connectors are required: one for the LVDS input interface in the upper left corner and the other for the LVDS output interface in the lower left corner. The display module circuit board can be embedded in the video display board frame, and all interconnect boards are mounted in the frame. No additional leads are required for the LVDS interface between adjacent LED display module PCBs.

3 Power consumption

Each MAX6974 operates at 28 mA (CALDAC off) or 54 mA (CALDAC enabled) when powered by 3.3 V VCC. An LED display module PCB contains 64 LED drivers operating at 1.8 A or 3.5 A. The maximum LED current provided by the MAX6974 per port is 30 mA when powered by 5 V VLED. The maximum current of a 512 RGB LED display module is 46 A, requiring multiple 3.3 V and 5 V supplies to power the entire video display board.