Codasip partners with Siemens to provide tracking solution for custom processors

The solution significantly increases productivity even in the most complex heterogeneous and customized designs

Munich, Germany, September 5, 2023 - Codasip®, the leader in RISC-V custom computing, announced that the company can now provide Tessent™ Enhanced Trace Encoder enhanced trace encoder solutions for its custom RISC-V processor cores . This solution is a member of Siemens EDA's Tessent Embedded Analytics embedded analytics product line. With this joint solution, developers can effectively track and debug issues between silicon and software and gain accurate visibility into the real-time behavior of the most complex custom designs based on Codasip RISC-V processor™ processors.

Codasip's RISC-V processors are fully customizable and adaptable to the unique needs of an application. System designers can use the Codasip Studio™ toolchain to find the best software and hardware trade-offs and achieve optimal functionality and PPA (power, performance, area). Combining customizable processor IP and tools for processor design enables an automated approach to customized computing. To make this customization service available to software developers, Codasip ensures that all tools support customization, including compilers and debuggers. Now also includes tracking solutions.

Adding trace capabilities to SoCs can significantly speed up the once time-consuming task of software debugging, thereby reducing project startup time and software development costs. Codasip chose to work with Siemens EDA to develop its Trace Encoder encoders because both companies believe in effectively achieving product quality throughout the entire product design process. This focus on quality enables innovation, helping customers significantly increase productivity even in the most complex heterogeneous and custom designs.

Tessent Enhanced Trace Encoder The enhanced trace encoder is based on the RISC-V standard developed by the Debug and Trace Working Group, which is led by representatives from Siemens, which donated the Trace algorithm to the RISC-V international community . However, Siemens’ solution goes well beyond the RISC-V standard, providing a more efficient tool that delivers significant productivity benefits in the development of the most complex systems and also supports custom instructions. It performs a detailed examination of the system to find errors and their root causes. It's cycle-accurate, which means developers have deep visibility into every instruction.

Mike Eftimakis, Vice President of Strategy and Ecosystems at Codasip, commented: “Codasip sets high quality standards for its processor IP. To ensure that the results support great systems, we needed a traceability solution that goes beyond the RISC-V standard. "The Tessent Enhanced Trace Encoder is optimized for the complex and customized systems our customers are developing."

“Tessent Embedded Analytics enables full-system, real-time debugging and post-deployment analysis, helping SoC providers focus on the critical task of producing high-quality, innovative products and bringing them to market quickly,” said Siemens said Ankur Gupta, Vice President and General Manager of EDA Tessent Division. “Codasip has an excellent reputation for helping customers meet these requirements, and we are delighted to be partnering with them.”

Codasip will offer its Tessent Enhanced Trace Encoder solution directly to customers to simplify contract complexity.