SX series communication controller

    Abstract: This article introduces the performance, internal structure, port characteristics and memory architecture of the SX system microcontroller, and explains the broad application prospects of virtual peripherals. The SX series microcontroller has high-speed operation and flexible I/O characteristics, and can be used as an embedded device in communication product design.

    Keywords: Embedded Internet device RISC structure configuration port state memory architecture virtual peripherals

SX52BD (and SX48BD) are SX series products, which are configurable communication controllers manufactured using CMOS technology. Its operating frequency can reach 50/75/100MHz, making it a high-speed computer; most of its instructions are single-cycle instructions, and its running speed can reach 20 times that of ordinary MCUs; its flexible I/O characteristics enable efficient real-time control Function. Because of its high-speed operation characteristics, the device can use software modules (virtual peripherals) to replace some of the real-time functions implemented by hardware in the past. This is the most important feature of the SX series. Currently, most of the virtual peripherals that can be implemented are used in communication equipment, such as communication interfaces and Internet connection protocols. The following mainly explains it from its hardware structure.

1 Main performance and features

①CPU performance. Based on the RISC structure, a compressed instruction system is adopted. Most of them except branch are single-cycle instructions. The operating frequency can reach up to 100MHz. At this time, the instruction cycle is 10ns and the internal interrupt response time is up to 30ns. The code can be read during runtime (IREAD instruction). ) for fast platform search; it can overcome the shortcomings of slow running speed of general MCUs and enable the internal program of the SX series to achieve the purpose of hardware real-time control function.

②Hardware peripheral characteristics. It contains 2 16-bit timers (with 8-bit prescaler) internally. The operating modes include software clock mode, PWM mode, synchronous PWM/capture mode and external event mode; one (with 8-bit prescaler) can Programmable 8-bit timer/counter (RTCC) and watchdog timer (shared RTCC prescaler); internal analog comparator included, which is very convenient for general applications.

    ③Due to the high-speed operation characteristics of the SX series and the flexible I/O functions, the device can use software modules (virtual peripherals) to replace the accurate real-time functions of those hardware. Currently, most of the virtual peripherals that can be implemented are used in communication equipment (such as communication interfaces and Internet connection protocols, etc.) and as signal generating devices and conversion devices that run at relatively high speeds.

④Programming and debugging support. The chip can be programmed online through the serial port or parallel port (for example, the oscillator pin can be connected for online serial programming), and the chip has online debugging support logic. For real-time simulation and full-scale debugging, a complete development environment can be provided by a third-party tool supplier. This software support includes ready-to-use virtual peripheral module libraries, comprehensive virtual peripheral examples, and application software toolkits for communications.

SX equipment can provide new ideas and solutions. On the one hand, it can be applied to some conventional equipment, such as: process controllers, electronic equipment/tools, security/monitoring systems, automotive users, power control systems, and private communications. equipment, etc.; on the other hand, the SX communication controller is the hardware platform of the SX stack, which can implement the entire TCP/IP protocol, physical layer and other related high-speed communication layers - virtual peripheral modules. Frontier's virtual peripheral library is also constantly expanding its application scope. For example, the emergence of Internet protocol stacks and communication interfaces allows designers to embed some products into the Internet. Its entire network connection protocol stack tool enables single-chip network servers and e-mail devices to be used in embedded applications. These tools include TCP/IP network connection protocol, physical layer and other related high-speed communication layers-virtual peripheral modules. Its virtual peripheral library is also constantly expanding its application scope. For example, the emergence of Internet protocol stacks and communication interfaces allows designers to embed some products into the Internet. Its entire network connection protocol stack tool enables single-chip network servers and e-mail devices to be used in embedded applications. These tools include a physical layer interface to the TCP/IP network connection protocol, allowing system designers to develop low-cost embedded Internet devices without having to use external physical pathways or PC gateways.

2 Circuit structure

Figure 1 shows the internal structure block diagram of the SX series products. It can be seen that the SX series products use two independent memories with different address buses internally, one for program and the other for data. The two are strictly separated. It allows data to flow from program memory to SRAM simultaneously, and data tables can be accessed from program memory. The advantage of this structure is that fetching instructions into storage transfers can be performed alternately through multiple layers of channels. This means that the next instruction from program memory can be fetched while the current instruction is being executed. In fact, this is a RISC-based structure. Its memory design process can make the device 20 times larger than the traditional MCU block, and it can accurately freely oscillate and can be programmed. SX series products use 4 stages of transfer (receive-decode-execute-write), so one instruction is executed per clock cycle. When the maximum operating frequency reaches 100MHz, instructions run every 10ns clock cycle.

The program memory uses EEPROM or Flash, with an on-chip capacity of 4,096 bytes, and the repeated writing cycle can be more than 10,000 times during use; while the data memory is SRAM, with an on-chip capacity of 262×8 bits.

In addition to the above notable features, its interface part also includes the following parts: 2 16-bit timers with 8-bit prescaler, which can support different operating modes (PWM mode, synchronous PWM/capture mode and external event counter mode ); 1 universal 8-bit timer with prescaler, 1 analog comparator, 1 brownout detector and watchdog timer; node mode with a multi-source wake-up function, port B (8 There is a wake-up/interrupt function on the pin); an internal RC oscillator allows the user to select the clock mode. The adjustable range of the RC internal oscillator is 31.25kHz~4MHz.

Currently, there are two products in the SX series, SX48BD and SX52BD. Except for the different pin packaging forms, other functions are basically the same. It can be seen from the two circuit outlines in Figure 2: SX48BD is a 48-pin package, and SX52BD is a 52-pin package. The difference between them is that the A port is different: the latter has 8 I/O pins, while the former only has 4.

3 port features

As can be seen from Figure 2, the SX series has five 8-bit I/O ports (i.e., port A ~ port E). The situation of port A is somewhat different from the other four ports. Figure 3 shows the internal situation of port A: the hardware structure and the configuration register of each pin of the port. Port A provides symmetrical drive capabilities. In the 48-pin SX48BD device, Port A only has 4 pins (instead of 8 pins). Each port has 4 corresponding 8-bit registers (ie, direction, data, TTL/CMOS selection and pull-up enable register) for configuring the status of the port pins. For example: select high-impedance input or output, or select TTL or CMOS voltage level, or select to turn on/off the pull-up resistor. According to the corresponding relationship between the lowest bit of the port pin and the lowest bit of the register, to access these configuration registers, a reasonable value must also be written to the MODE (mode) register at the same time.

When powering on, all bits in the register are initialized to "1". Under software control, the relevant registers configure each port bit, as shown in Figure 4.

Different from the situation of port A, ports B, C, D and E have additional related registers (Schmitt trigger enable register) that can enable or disable the use of Schmitt triggers on each port pin. Port B supports the differential comparator on the chip. The RB1 port and RB2 port are the negative and positive input pins of the comparator respectively, and the RB0 port is the output pin of the comparator. In addition, Port B also supports multiple input wake-up functions on all 8 pins. Ports B and C also support multi-function timers T1 and T2; RB4 and RB5 are the capture input pins of T1, and RB6 is the PWM output pin of T1; RB7 is the external event counter input pin of T1; similarly, RC0 and RC1 is the capture input pin of T2, RC2 is the PWM output pin of T2, and RC3 is the external event counter input pin of T2. Figure 5 shows the hardware structure of ports B, C, D, and E and the configuration register of each pin of the corresponding port.

4 Memory architecture

Program memory - consists of 4K words of 12-bit width. Program memory words are addressed by the binary program counter. On reset, the program counter is initialized to 0FFFH. If there is no branch operation, it will increase to the maximum size of the device and the cycle will continue. 1 page consists of 512 adjacent program memory words. At the first address of a page, the lower 9 bits of the program counter are all "0"; and at the last address of the page, the lower 9 bits of the program counter are all "1". This page structure has no effect on the program counter, which will continue to increase through pages.

Program counter - contains the 12-bit address of the executed instruction, the lower 8 bits are stored in the PC register (02h), and the 3 upper bits are specified by the status register STATUS (PA0, PA1, PA2), and the 8th bit is not used. Changing the status bit will cause jumps between program memory pages and subroutine calls. To prioritize branch operations, the user program must initialize the high bits of the status register to transfer to the desired page. Another way is to use the "page" instruction, which automatically transfers the address to the desired page according to the specific value of the operand.

Subroutine stack - contains 8 12-bit storage registers. Regulations can affect the stack during physical transfers of register contents (such as from the program counter to the stack and vice versa and within the stack), especially call and return operations. The stack is physically and logically separate from the data RAM, and programs cannot read or write to the stack.

Data memory - is a RAM-based register, including 262 commonly used registers and 9 special function registers, so these registers are all 8 bits wide. The data memory is divided into 16 layers, from 0 to F. Each layer contains 16 registers, plus an additional layer of 16 "global" registers. Since these registers are composed of layers and "files", these memory mapped registers are called "file registers".

Addressing mode - Each SX instruction that accesses the data storage memory contains a 5-bit opcode instruction, which is used to specify which register is accessed. The abbreviation "fr" (file register) represents the 5-bit register address identifier. For example: In the "mov fr, W" instruction, "fr" represents a 5-bit value or flag, such as the "mov $ OF, W" instruction (moves the contents of the working register W to the file register 0Fh).

There are 3 different addressing modes: indirect addressing, direct addressing, and semi-direct addressing. The selection of register addressing mode depends on the value of the 5-bit "fr" in the instruction, for example:

*Indirect mode: fr=00h

*Direct mode: (fr bit 4=0)fr=01h-0Fh

*Semi-direct mode: (fr bit 4=1) fr=10h-1Fh

The block diagram of the data memory is depicted in Figure 6.

For indirect addressing mode (fr=00), the file select register (FSR) specifies the register to be accessed. The FSR is an 8-bit storage mapped register (address 04h). In indirect addressing, it acts as an 8-bit pointer to data memory. In this mode, the global register layer and layer 1 to layer F are available, but layer 0 is not available.

For direct addressing (fr=01-0F), the value of "fr" itself indicates the register to be accessed, and the FSR register is ignored. For this addressing mode, only the global register level is accessed; to access any other level, indirect or semi-direct addressing must be used.

For semi-direct addressing (fr=10-1F), the layer number is selected by the 4 high-order bits of FSR; and the register within the layer is determined by the low-order 4 bits of "fr", that is, the register address is determined by the 4 high-order bits of FSR. The high bit and the four low bits of "fr" are determined together. In this addressing mode, the low bits of FSR are ignored and can be accessed from layer 0 to layer F, but the global register layer is not accessible.

Figure 6 lists how registers are addressed in indirect, direct, and semi-direct modes. Regardless of the value in the FSR register, all 16 global registers are accessible during direct addressing. Global registers can also be accessed in indirect addressing mode, but not in semi-direct mode. Among these 16 global registers, 9 are special function registers (RTCC, PC, STATUS, etc.) and 6 are global registers. 00 is used for indirect addressing (INDF). All registers from layer 0 to layer F are global registers. To change the value in the FSR register, the program can either write an 8-bit value in the FSR register or use the "layer" instruction. The layer instruction can write to bits 4, 5 and 6 of the FSR register, and bit 7 is used to select the upper or lower layer of the storage layer. Therefore, if you want to change the upper layer to another upper layer, you only need to use a "layer" instruction; if you want to change the upper layer to the lower layer, the "setb FSR.7" instruction must be used after the "layer" instruction.

5 Concept of virtual peripherals

The concept of virtual peripherals enables the realization of "chip software systems", that is, using software modules to replace traditional hardware peripherals to achieve the same effect as hardware devices. Due to the use of virtual peripheral libraries and good speed and flexibility, it provides a broad path for engineering and product development. It can greatly reduce the product development cycle and shorten the product development cycle. The virtual peripheral library can provide system designers with some predetermined solutions or provide system designers with preconceived ideas when developing peripherals. With the functions supported by virtual peripherals, designers only need to focus on other applications. Due to the continuous development of standards and protocols, virtual peripherals combined with online reprogramming capabilities provide powerful development prospects for the communications industry. In summary, virtual peripherals have the following advantages: simple use of equipment, reduction of component count, rapid entry into the market, increased design flexibility, compatibility with most machines and reduced cost of the entire system.

Examples of virtual peripherals that can be implemented are:

*Some common communication interfaces such as: I2C, microbus ( μ -level bus), SPI, IrDA stack, UART and modem functions.

*Internet connection protocols, such as: UDP, TCP/IP, HTTP, SMTP, POP3, etc.;

* Frequency signal generation and debugging;

*Generation of PPM/PWM;

* Δ- ∑ADC;

*DTMF generation/detection;

*FFT/DFT algorithm.

Due to the structure of the SX series hardware structure and virtual peripheral concept, it provides a powerful and flexible development platform for the communication development department; due to its high processing power and flexible structure, it has relatively high cost-effectiveness. . Strong development capabilities can give designers enough confidence to keep up with standards and innovations in many fields and develop a large number of future communication control products.