Design plan for communication between '54x series DSP and computer parallel port-EEWORLD

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Abstract: Data communication between digital signal microprocessors and computers is receiving more and more attention. This article mainly introduces a simple design scheme for TI's '54x series DSP to communicate with the computer parallel port through the main interface (HPI). This solution achieves stable data transmission with a simple circuit design and has high communication speed.

Keywords: DSP TMS320VC5410 host interface (HPI)

Digital signal microprocessor (DSP) is a new technology that has emerged in the past decade. With its fast speed and powerful functions, DSP has gradually entered the industrial and consumer fields occupied by traditional microcontrollers. TMS320C54x (referred to as '54x) is a new generation of high-performance DSP chips launched by Texas Instruments Inc. (TI Inc.) following TMS320C1x, TMS320C2x, and TMS320C5x. This series of chips has the advantages of low power consumption, high performance, and high cost performance, and is widely used in image processing, voice processing, instrumentation, communications, multimedia, military and other fields.

In many data collection and control systems with PC as the terminal, due to the strictness of the communication protocol, the peripheral microprocessor not only needs to complete data collection and control, but also needs to be responsible for communicating with the PC host and transmitting data, etc. Task. This burden becomes even more prominent in high-speed data collection. Most of the solutions are to add devices dedicated to host communication. Due to the integration of many powerful functions, '54x can not only achieve high-speed data acquisition and control, but also almost complete communication with the host without increasing burden.

1 Main features of the '54x

The '54x series, characterized by high speed and low power consumption, adopts an advanced modified Harvard structure, with separate data bus and program bus, and integrates ROM, RAM and multiple peripherals on-chip, such as general-purpose I/O ports, Timers, clock generators, software programmable wait state generators, programmable block switching logic, serial ports, direct memory access controllers (DMA), and host port interfaces (HPI, Host Port Interface) for communicating with external processors ).

2 '54x Host Interface (HPI)

There are three main host interfaces (HPI) in '54x: the standard 8-bit HPI-8 interface, the enhanced 8-bit HPI-8 interface, and the 16-bit HPI-16 interface. Among them, '542~'549 contain standard HPI-8, '5402 and '5410 contain enhanced HPI-8, and '5410 and above are HPI-16; while the HPI of '5409 and '5416 can be set to enhanced HPI by the user. HPI-8 or HPI-16, the enhanced type is superior to the standard type mainly in that the enhanced type allows the host to access all on-chip RAM inside the DSP, while the standard type can only access the 2K words specified in the RAM area.

Take the enhanced HPI-8 interface included in TMS320VC5410 (abbreviated as '5410) as an example. Its connection with an external host or microprocessor is shown in Figure 1. It has 8 separate data lines HD0~HD7 and 10 control lines. Wire. The timing logic of the control signal is shown in Figure 2. The host actively accesses the DSP through the HPI port. In addition to sending an interrupt to the host (by setting the HINT bit in the HPIC register, the HINT line can be enabled) or clearing the interrupt from the host (by clearing the DSPINT flag in the HPIC register), DSP intervention is required. The 5410 CPU hardly needs to perform other operations. The on-chip DMA channel will automatically assist in completing the data transfer of the RAM area and HPI data register. The host determines to select a certain control register of HPI by the HCNTL0/1 line, as listed in Table 1. By accessing these four registers, you can read/write all or part of the on-chip RAM of the DSP within the allowed range of the set security mechanism.

Table 1 HCNTL0/1 selection function description

HCNTL1	HCNTL0	describe
0	0	Host read/write HPI control register--HPIC
0	1	The host reads/writes the HPI data latch - HPID in the address auto-increment mode. If it is a read operation, the HPI address register HPIA will automatically increase by one unit after each read; if it is a write operation, HPIA will automatically increase by 1 after writing.
1	0	The host reads/writes the HPI address register--HPIA, which points to the on-chip RAM address of '54x
1	1	Host reads/writes HPI data latch - HPID, HPIA remains unchanged

Since the smallest storage unit of DSP is a word (16 bits), for HPI-8, each transfer must have 2 transfer cycles to complete. The HBLL signal is used to distinguish whether the transferred byte is the first byte or the second byte of the current word. By setting the BOB bit of the HPIC register, you can decide whether the first byte is the high byte or the low byte of the word.

Program downloading through HPI is one of the five ways of '5410 program loading. In application designs that need to be connected to the host, using the HPI program loading method can simplify the circuit design and eliminate the need for external parallel or serial ROM or FLASH program memory.

3. Connection between enhanced HPI-8 and host parallel port

'5410 has most of the features of the C54x series, including 3 multi-channel buffered serial ports (McBSP) six-channel DMA, 8-bit enhanced host interface HPI-8, enhanced external parallel interface (XIO2), and 16K words of on-chip ROM , 56K words of on-chip RAM, etc., it can be said to be a powerful microprocessor.

When implementing parallel port communication between the DSP and the computer host, set the working mode of the host parallel port to the extended function (ECP) mode. In situations where the communication rate is not high, it can be set to PS/2 mode. PS/2 mode is a bidirectional transmission mode extended on the basis of SPP, which reads/writes data in bytes.

In some designs of parallel port communication between DSP and host, CPLD is used to generate interface timing. This method not only increases the circuit cost, but also adds complexity to the design. In fact, parallel port communication between the DSP and the host can be achieved using a few simple logic gates.

For the host parallel port line of DB25, Data0~Data7 are used as dual HDS1 control signals, and AudoFd and SelechIn are used as HCNTL0/1 signals respectively. Init serves as the HR/W control signal. The HBIL signal is triggered by the Strobe signal to flip the JK flip-flop. Considering the program loading function of HPI, the JK flip-flop is used to logically combine the SelectIn and AutoFd signals to obtain the RESET reset control of the DSP. In addition, the '5410's I/O port line is 3.3V CMOS voltage, while the parallel port is usually 5V TTL voltage. Therefore, in order to achieve level matching, a voltage conversion buffer SN74LVC245 is added between the two stages. The specific circuit design is shown in Figure 5.

The state change rules of HCNTL0/1 are shown in Figure 4. It can be seen that only when HCNTL1 is 1 and HCNTL0 changes from 0 to 1, the reset state flip will be triggered. Therefore, when it is necessary to switch from register HPIA to non-incrementing HPID, in order to avoid triggering the reset state flip, HCNTL1/HCNTL0 should be converted in the manner of 10-00-01-10.

4 Programming

4.1 Host program

The host program mainly completes the selection of HPI registers, construction of timings, and data reading/writing. Due to space limitations, here we only list the timing construction of the host reading the DSP on-chip RAM storage area and the communication handshake with the DSP. Among them, p_DATA, p_STATUS, and p_CONTROL represent the data register, status register, and control register of LPT1 respectively. Bits 7~5 of the ECP extended control register ECR are set to '001'. HPI's HPIC register BOB bit is set to '0' (the first byte is the high byte).

/*Read/write HPI register, the read/write 'word' is stored in *data and *(data+),

When r_w is 0, it represents writing, and when it is 1, it represents reading. */

void HPIregRW(char*reg,BYTE*data,BYTEr_w)

{

BYTE test;

BYTE CRW=0x00|(r_w<<5);

int i_HBIL=0;

/*Switch to select one of the HPIC, HPIA, HPID_I, HPID_n registers*/

if(strcmp(reg,"HPIC"==0)

{

ChangeCONTROL(0x0b|CRW);

//ChangeCONTROL(BYTE bValue)

}

else if(strcmp(reg,"HPIA"= =0)

ChangeCONTROL(0x03|CRW);

else if(strcmp(reg,"HPID_I"= =0)//Use auto-increment address host to write

ChangeCONTROL(0x09|CRW);

else if(strcmp(reg,"HPID_n"= =0) //Host write

ChangeCONTROL(0x01|CRW);

else

{

printf("Wrong register for HPI write.";

exit(-1);

}

outp(p_CONTROL,CONTROL);

if((_inp(p_STATUS)&0x08)!=0) //If HBIL! =0

{

ChangeCONTROL(0,0); //Overloaded function

//ChangCONTROL(BYTE bit,BYTE bValue)

_outp(p_CONTROL,CONTROL); //HDS1=0

ChangeCONTROL(0,1);

_outp(p_CONTROL,CONTROL); //HDS1=1

}

/*Preparation for starting sequence*/

while((_inp(p_STATUS)&0x08)!=0); //Wait for HBIL=0

//(lst byte)

if(r_w)//read

{

//Sample the data line (first byte) on the rising edge of HPIR/W

ChangeCONTROL(2,1);

-outp(p_CONTROL,CONTROL);

ChangeCONTROL(0,0);

_outp(p_CONTROL,CONTROL);//HDS1:1->0, //Sampling HCNTL0/1, HR/W, HBIL

while(_inp(p_STATUS)&0x10= =0); //If HDRY=0, //wait; HDRY=1, continue

ChangeCONTROL(0,1);

outp(pCONTROL,CONTROL);//HDS1：0->1; //Latch the 1st byte, then HBIL=1

*(data++)=_inp(p_DATA);

while((_inp(p_STATUS)& 0x08)= =0); //Waiting for HBIL//=1(2nd byte)

ChangeCONTROL(2,0);

_outp(p_CONTROL,CONTROL);

//Sample the data line (second byte) on the rising edge of HPIR/W

ChangeCONTROL(2,1);

_outp(p_CONTROL,CONTROL);

ChangeCONT^ROL(0,0);

_outp(p_CONTROL,CONTROL);//HDS1:1->0,

//Sampling HCNTL0/1, HR/W, HBIL

while(_inp(p_STATUS)&0x10)= =0);//If HDRY=0//Wait, HDRY=1 to continue

ChangeCONTROL(0,1);

_outp(p_CONTROL,CONTROL); //HDS1: 0->1; //Latch the 2nd byte, then HBIL=0

*(data- -=_inp(p_DATA);

while((_inp(p_STATUS)&0x08)!=0); //Wait for HBIL=0

(lstbyte)

ChangeCONTROL(2,0);

_outp(p_CONTROL, CONTROL);

}

else//Write {(omitted)}

}

…

void main(void)

{

/*HPI initialization*/…

/* Wait for the DSP to send an interrupt HINT (query mode) to the host, then read from the DSP */

WriteHPIreg("HPIC",0x0808); //Clear HINT interrupt

/*Read DSP on-chip RAM area data*/

for(i=0;i

{

HPIA=resultAddr++;//resultAdd: RAM number to be read//starting address of data area

WriteHPIreg("HPIA",HPIA);

while((_inp(p_STATUS)&0x40)!=0); //Waiting for DSP to send//send HINT valid signal (handshake signal)

//Call the function to read the data in the RAM area and write the created file data.dat

WriteHPIreg("HPIC",0x0808); //Clear HINT interrupt

WriteHPIreg("HPIC",0x0404); //The host sends DSINT to the DSP (handshake signal)

}

WriteHPIreg("HPIC",0x0808); //Clear NINT interrupt

}

Tests have shown that the reading speed of the host parallel port is much lower than the execution speed of the DSP. Therefore, some waiting query instructions in the program sub-functions can be omitted. In the main function main(), if the DSP data read is static and does not need to be provided in real time, such instructions can also be omitted.

4.2 DSP handshake procedure

In actual situations, most of the data that needs to be transmitted is processed by DSP in real time. Processing and transmitting at the same time can greatly improve the overall efficiency of the system, and due to the characteristics of HPI work, transmission can take up almost no DSP time. The only thing that requires DSP intervention is to notify the host to receive the data (via HINT interrupt) when the data is ready. This task can be carried out in the DSPINT interrupt service routine of the amplified DSP. The program is briefly as follows:

.mmregs

.include "vectors.h"

dataarea .usect "COMMS",100h,1;The data block range to be transferred

HOSTACK.macro

hack ldm hpic,a ; Accumulator A loads HPIC value

and #08h,a ; shield other bits of HINT

bc hack,aneq; Determine the status of HINT until HINT

; bit is 0 (that is, the host clears the HINT flag)

.endm

.text

start:stm #00a0h,pmst; set IPTR register

stm #0000h,st0 ;Set ST0 and ST1 registers