Design scheme of CAN adapter card in generator condition monitor

    Abstract: This article introduces the function and hardware composition of the CAN intelligent adapter card in the generator status monitor. Aiming at the arbitration problem when the ISA and Hum microcontroller simultaneously read and write data to the dual-port RAM, a hardware arbitration implementation method is proposed. , and gave an overall explanation of the software design of the adapter card.

    Keywords: Adapter card IDT7132 Dual-port RAM SJA1000

CAN (Controller Area Network) control area network is a serial communication network. It uses many new technologies and unique designs, giving it outstanding advantages in reliability, real-time performance and flexibility. These excellent performances enable the CAN bus to maintain rapid development worldwide. Taking into account the growth of CAN bus and the fact that many microcontrollers integrate CAN bus controllers, and the CAN bus dedicated controller IC technology is easily available on the market, therefore, CAN bus technology is used in the generator status monitor designed by the author.

1 Composition model of CAN bus system

The fieldbus-based generator status monitor consists of three parts: an intelligent data acquisition module, an industrial personal computer (IPC), and a CAN bus. Its system structure is shown in Figure 1. Each module communicates with an industrial computer system through the CAN bus. The main function of the industrial computer is to set the parameters of the intelligent data acquisition module and obtain the data of the intelligent data acquisition module in real time through the field bus network, such as generator event recording and fault recording; real-time display, trend analysis, and abnormal monitoring data Functions such as alarming and completing report output. The CAN bus part is mainly composed of CAN bus adapter card, communication medium and corresponding communication software.

2 Hardware structure of CAN smart adapter card

The excellent performance of the CAN bus provides guarantee for high-speed data communication of the generator status monitoring system. However, many industrial PCs do not have a CAN bus interface. In order to expand the monitoring and management functions of the CAN bus on the IPC, the author designed a suitable The matching card is inserted into the expansion slot of the IPC to complete the expansion functions of the CAN interface and IPC.

The hardware circuit of the CAN bus PC adapter card is shown in Figure 2. It mainly includes the 89C52 microcontroller (containing 8K E2PROM, 256 bytes of RAM), address decoding and interrupt signal control logic circuit EPM7128S, and shared memory dual-port RAM (IDT7132 ), CAN controller SJA1000 chip and photoelectric isolation circuit (6N137) and CAN driver 82C520.

To realize data transmission between the PC and the CAN controller, a bidirectional data exchange channel must be established between the PC and the MPC on the adapter card. There are two ways to implement data exchange between the microcontroller system and the host through the ISA bus: one is static data transfer, which uses parallel interface devices (such as 8255) or latches (such as 74LS373) to form a byte depth FIFO. This method is relatively simple, but the amount of data transmitted at one time is small, so it is only suitable for situations where the amount of data is small and the speed requirements are not high; the second is to share the external data memory of the microcontroller system. At this time, the integrated dual-port RAM can be directly used or some control logic can be added to the general-purpose RAM to form a dual-port RAM circuit. Integrated dual-port RAM is a fast pass device with excellent performance, suitable for multi-CPU distributed systems and high-speed digital systems. It provides two completely independent ports, each with complete address, data and control lines. For users of the device, it is not much different from ordinary RAM. Contention occurs only when both sides read and write the same address unit at the same time. Utilizing dual-port RAM to provide indication signals and adopting appropriate communication rules can avoid contention and achieve fast data exchange. Integrated dual-port RAM is not only easy to implement, but also inexpensive. CAN signal transmission uses a short frame structure (8 bytes), and the adapter card does not require a large capacity for dual-port RAM, so IDT7130, IDT7132, IDT71231, etc. can be used. This article uses the 2k×8-bit IDT7132 with busy signal BUSY. The CAN communication controller uses the SJA1000 produced by Philips Company that supports the CAN2.0B protocol and is fully compatible with the 82C200. If it is regarded as a memory-mapped register, it is easy to interface with the 89C52. In order to enhance the differential sending and receiving capabilities of the CAN bus, this design uses the CAN bus transceiver interface circuit 82C250. Connecting an optocoupler between the SJA1000 and the slave's 82C250 can enhance the system's anti-interference capability. The optocoupler can use high-speed optocoupler 6N137. The application on both sides of the optocoupler uses DC-DC isolated power supply, and the PS250DC5D5S produced by Liyuan Company can be selected.

3. Stretching method

The key to the dual-port RAM communication method is to handle the contention phenomenon and avoid the resulting read and write errors. IDT7132 can provide hardware arbitration method and can use the signal of BUSY pin to improve the flexibility of the system. In the hardware circuit of Figure 2, because IDT7132 contains a hardware arbitration circuit and the ports on both sides have BUSY pins. Therefore, when two ports compete for the same address unit, the on-chip hardware circuit can determine which port has the right to use based on the address, chip select and read and write signals on both sides arriving in the post-selection sequence.

It can be seen that the BUSY signal can be directly sent to the READY pin of a CPU that supports insertion of wait sequences, such as the 80C196, without software support. In this card, since the 89C52 does not have a READY signal, the BUSYR signal will be latched when the 89C52 issues a read or write command to the IDT7132. You only need to read the value of the P1.6 port to determine whether there is a conflict when reading or writing the IDT7132 just now. When the value of P1.6 is 1, there is no conflict in the inquiry just now; when the value of 1.6 is 0, there is a conflict with the Public Security Department in the inquiry just now. At this time, the command to read and write IDT7132 needs to be reissued. Since the ISA bus has no READY signal and no general-purpose I/O pins, the BUSYL signal from the IDT7132 can be connected to the lowest bit D0 of the data line. However, because BUSYL should not be connected to D0 except when querying the BUSYL pin level, the three-state gate 74L125 should be used. BUSYL is connected to the input terminal of the tri-state gate, and the output terminal of the tri-state gate is connected to the D0 bit of the ISA bus data line. Its gate control signal is generated by A9~A5, so it will occupy an I/O port of the ISA bus. When designing, an idle port number should be selected. Here we choose 330H (dual-port RAM side, PC needs to change the code), that is, A9 ~ A5 are decoded to 11001. The specific circuit is shown in Figure 3.

4 Software design of adapter card

The adapter card is mainly used to undertake the data forwarding task between the host computer and the CAN node. Its software design also includes two parts: The first part is the application program interface (API) function of the PC side, which is responsible for completing the PC side and the dual-port RAM. The communication between them can be written using visual programming tools such as C++Builder. PC software functions mainly include sending control commands, data commands and request data commands to the dual-port RAM on the adapter card, and also post-processing the received data (such as display, reports, etc.); the second part is the card The program design on the microcontroller side is responsible for the communication between the microcontroller and the dual-port RAM to dominate the CAN controller. This part can be written in assembly language ASM51 or Franklin C51. The main task of the software design is to forward commands from the PC to the CAN controller. , and further forwarded by the CAN controller to the CAN node; at the same time, the data and status information received by the CAN controller from the CAN node are sent to the dual-port RAM.

5 issues that need clarification

The CAN protocol specification (CAN Specification 2.0A/B) is only a low-level specification. Therefore, a high-level/application-layer protocol is also needed, and the capabilities of CAN are selected and limited by the high-level protocol. Currently, there are many CAN application layer protocols in the world, such as DeviceNet, CANopen, CANKingdom, etc., but users can customize simpler application layer protocols. On the one hand, the task of the application layer protocol is to classify, disassemble, and merge the data to be sent, and determine the sending object, and then fill in each information frame of CAN according to the CAN data link layer protocol specification. The other aspect is to interpret the specific meaning of the received data and process it accordingly.