Application of I2C Interface in Imaging System

Reading data from exposure register 0x09: The beginning part is the same as the timing of writing data. After the master device sends the slave device address (write mode) and the register address, it needs to restart and send the slave device address (read mode) before reading data from the register. After reading each byte of data, the master device will generate a 1-bit response signal. When 16 bits of data are read, the master device sends a 1-bit non-response signal and the transmission ends.

3 IP Application Examples

3.1 Hardware Design

This article uses I2C control IP to configure the image sensor MT9M011 register in parallel. The hardware design is based on SOPC technology, integrating the 32-bit Nios II soft-core processor, SDRAM interface module, TIMER timer module (providing the frequency of signal sampling in SignaltapII), PIO module and I2C control IP (configured as a master device) provided by the system component library into an FPGA. QuartusII top-level principle is omitted - Editor's note.

3.2 Software Design

There are two ways to write software: one is to operate the I2C control IP application programming interface (API) function; the other is to use the read and write functions provided by Altera to operate the register. In order to improve the speed of system operation, the second method is adopted. The system software part is completed by writing C code in NiosII IDE.

The parallel configuration procedure for CMOS registers mainly includes the following two parts:

①IP initialization settings: including setting the baud rate, setting the local address register, and setting the clock register value.

② Select CMOS1 to read and write its register; select CMOS2 to read and write its register. Register selects exposure register.

The key codes are as follows:

The checkBus function queries the status register to determine the busy/idle status of the I2C bus, and the checkProgres function queries the status register to determine whether the bus data has been transferred. In order to observe whether the read data is consistent with the written data, the program is usually included in a while statement.

4 Experimental Verification

Burn the download file generated by the hardware system to the FPGA chip and run the C code program. Use the SignahapII logic analyzer that comes with QuartusII to observe the data on the I2C bus. Figure 3 shows the waveform obtained. The signals from top to bottom are the I2C bus signals m_sclk_2, m_sda_2, m_sclk_1, and m_sda_1 on CMOS2/CMOS1. The first half writes 0x06 and 0x07 to CMOS1 and then reads it out; the second half writes the same number to CMOS2 and reads it out. This waveform meets the timing read and write requirements of the MT9M011 image sensor.

5 System Expansion

In applications that require multi-channel CMOS configuration, the I2C control IP can be used to easily implement multi-channel parallel CMOS register configuration. For example, an 8-channel parallel CMOS configuration system: 8 CMOS sensor chips are soldered on the circuit board, and the enable is loaded in parallel to the 8 CMOS chips by controlling the 3-channel signal of the distributor. The 3-channel control signal and the enable signal are realized by controlling the PIO interface module of the SOPC system, and the transmission of the configuration data is completed under the control of the I2C control IP. The circuit board structure is simple and the system is easy to implement.

Conclusion

The I2C IP introduced in this article can be loaded into the SOPC system as a custom component, making the system design more flexible and having great potential for functional expansion. In the imaging system using CMOS image sensor, the I2C interface is widely used. This article gives an application example of the IP to illustrate that the use of the IP has broad prospects and high application value.