Application of DSP Technology in Mobile Communications

There are two main trends in the current mobile terminal architecture. One is to emphasize the flexibility of using programmable DSP in the face of ever-changing standards; the other is to emphasize the high efficiency achieved by using application-specific integrated circuits (ASICs). In the future, these two aspects will inevitably be combined.

Application of DSP in GSM

The functional block diagram of GSM is shown in Figure 1. In the figure, in GSM phase 1, the encoder uses short pulse excitation linear pre-coding technology to compress speech to 13Kb/s. Most hardware engineers believe that the speech encoder should be implemented by DSP. Now, DSP has begun to take on other functions of the physical layer in the functional diagram shown in Figure 1.

Flexibility is very important in evolving standards. GSM Phase 2 introduced Enhanced Full Rate (EFR) and Half Rate (HR) speech coding. Half Rate achieves the same speech quality with a higher compression rate of 5.6Kb/s, but at the expense of increased complexity. Enhanced Full Rate provides better speech quality and performance at the expense of higher complexity, which is achieved by applying an algorithm called Vector Sum Excited Linear Prediction (VSELP).

With these changes, the physical layer has improved performance, reduced costs, and reduced power consumption. Therefore, the physical layer of each generation of mobile terminals has some minor differences from the previous generation, and upgrading ASIC-based solutions is more difficult and costly. Because there are now low-power DSPs designed specifically for wireless applications, the power savings of using ASICs to implement the functions performed by DSPs are not enough to make system designers give up the flexibility of using DSP designs.

With the evolution of GSM mobile terminals, they have gradually developed to realize more than simple telephone functions, which makes it possible to use DSP not only in the physical layer but also in other layers. Especially with the advent of the third generation of mobile communications and the application of wireless data services, this trend will accelerate.

DSP's development trend towards low power consumption

The enhanced structure, design and processing power of the new generation of DSP provide better performance and lower power consumption, suitable for battery-powered applications. We know that many communication algorithms are multiplication and accumulation (MuAcc) operations. So we use mW consumed per million MuAcc to evaluate the power consumption of DSP. According to statistics, the power consumption of DSP is reduced by half every 18 months. Due to the static logic used in DSP, the main power consumption is the charging and discharging of the internal capacitor of the device. This dynamic power consumption is shown in the following formula:

p=ac×V swing×V power supply×f

In the above formula, P represents the power consumed, a represents the number of cycles of the internal node in each clock cycle, v swing is equal to v power supply, and f represents the frequency. The dynamic power consumption of the entire chip is the sum of P of all nodes in the circuit. From the above formula, we can see that since the dynamic power consumption of each node is proportional to the square of the power supply voltage, it is very important to reduce the power supply voltage to save power. However, it is imperfect to simply reduce the power supply voltage without improving the technology. Therefore, while reducing the power supply voltage, it is also necessary to improve the technology to improve performance and reduce power consumption.

Below we take TI's TMS320C54x as an example to introduce its low power design. TMS320C54x is a DSP chip designed specifically for wireless communication applications. In addition, with the continuous growth of the wireless market, several other DSP chips designed specifically for wireless applications have appeared on the market.

The structure and instruction set of C54x are designed with power saving features. C54x uses an improved Harvard structure with three data storage buses, one program storage bus, two data address generators and one program address generator. This structure allows data to be accessed simultaneously, which is suitable for multi-operand operations, thus reducing the number of cycles required to complete the same function.

Another strategy for saving power in the C54x is to add special instructions that can execute important algorithms in wireless applications. There is also a compare select storage unit (CSSU) that greatly speeds up the Viterbi decoding speed.

The C54x instruction set also includes several special instructions, including: single instruction repeat and instruction block repeat, conditional instructions, Euclidean distance calculation, FIR (finite impulse response) and LMS (least mean square) filter operation instructions, etc. All of these are convenient for currently using DSP to complete the VSELP in the IS-54/136 standard, consuming 7.4mW power and 1.3mW power in GSM voice coding.

Power management is very important in low-power DSPs. C54x uses a hybrid power management strategy, namely active internal clock control and three user-controlled idle modes: shutting down the CPU, shutting down the CPU and chip peripherals, and shutting down the entire device with only memory status. The combination of a digital phase-locked loop-based clock generator and a DAC allows users to optimize the frequency and power consumption of their applications.

Application and structure of future mobile energy communication devices

Cellular communications have experienced several development trends since they were commercialized in 1983. The most important one is the development from analog to digital, which has increased the capacity of the system and the number of users, driving the demand for powerful DSPs.

The dual-processor structure used in traditional cellular phones is actually a simple modem. In the future, terminals that focus on data services will have new structures. They must increase processing resources to support increasingly complex user interfaces, handle more complex data services in addition to voice, and more complex application environments. One solution is a DSP core plus a coprocessor structure, and another structure is multiple DSPs plus additional hardware to accelerate complex processing.

In short, low-power DSP will be more widely used in future mobile communications.