Design Method of Stable Operation of 51 Single Chip Microcomputer in Microcomputer Automatic Switching System

In power line carrier communication, the microcomputer automatic disk has many functions and strong logic. The real-time performance of the MCS-51 single-chip microcomputer when processing tasks in this system is particularly prominent. Since the main service object of the system configuration is power dispatching, and its use environment will mostly be unmanned stations in the future, the stability of the system operation directly affects the overall performance of the power line carrier machine. In view of the characteristics of power communication, we have taken the following measures to consider stable operation.

1 Set the power-on delay reset circuit

1.1 Why do we need to perform a power-on reset?

Computers must be reset when they start running. As the most widely used single-chip microcomputer in the control field, reset processing is the key in the design. Each functional component inside the single-chip microcomputer is controlled by a special function register, and the program operation is directly directed by the program counter. The reset state of the register determines the initial state of the relevant functional components in the single-chip microcomputer, and the normal operation of the program starts from this state. If the reset is not done correctly when the power is turned on, the CPU may start to execute instructions from an indefinite address, and the system will not be initialized correctly and cannot work normally.

1.2 Reset conditions

The microcontroller is reset by an external circuit. Power-on reset steps:

(1) The power supply Vcc must be established first;

(2) After Vcc stabilizes (reaches the allowable value), the clock oscillator starts oscillating;

(3) The reset pin must maintain the reset level for at least two machine cycles after the oscillator starts oscillating. In other words, the reset level maintenance time of the reset pin (RST) should include the Vcc establishment time, the oscillator start-up time and at least two machine cycles.

1.3 General power-on reset circuit

When powered on, the power supply Vcc should be established in less than tens of milliseconds. The oscillator start-up time depends on the oscillator frequency. For a 10MHz crystal, the start-up time is 1ms, and for a 1MHz crystal, the start-up time is generally 10ms. At this time, a general power-on reset circuit can be used (Figure 1).

If the power supply Vcc is set up to run very slowly, the RC power-on reset circuit will not guarantee reliable reset of the system. If the settling time is 1s, the RC charging curve is shown in Figure 2. At this time, it is difficult to make the RC circuit output a normal reset level (as RC charges, the potential ΔVc of the RST pin becomes lower and lower. After the power supply is stable, the amplitude of ΔVc does not meet the reset level requirements of the two machines, and the RST pin may exit the reset state). Moreover, the RST pin is easily affected by power supply interference and may cause false reset.

1.4 Power-on delay reset circuit

Although the power supply of power line carrier machines now adopts the switch working mode, the establishment speed is faster than the previous series or parallel adjustment power supply, but because the machine itself uses many voltage levels and has high power requirements, it takes at least 500ms for the establishment of various power supplies to stabilize after startup (+5V power supply is no exception), so it is almost impossible to meet the reset requirements in time by using general power-on reset in the automatic switching system. This is because the general power-on reset circuit of MCS-51 requires the power supply to be established within at least 20ms to ensure reset. This is a hardware feature. In order to overcome this delay difficulty, it is impossible for us to quickly establish all power supplies (this product must use the power supply of the matching equipment). We can only take corresponding measures in system design based on the characteristics of MCS-51 itself.

The MCS-51 hardware reset must ensure that after Vcc is stable and the oscillator starts oscillating, a high level of at least two machine cycles (24 oscillator cycles) appears at the RST terminal, that is, an internal reset is performed. For this reason, we designed a power-on delay circuit, which can change the R and C parameters according to the length of the power supply establishment time, and can adjust the delay time. Due to the use of this circuit, in the unattended station, the system will not "freeze" due to power failure and power on again, causing communication interruption, as shown in Figure 3. R1 and R2 provide comparison potential (2/3Vcc), the RC charging time is determined by the R and C parameters, R4 is the edge correction of the recovery signal, the V1 diode is the discharge circuit of the capacitor C when the power is frequently on, and V2 and the Watchdog circuit are logically in an OR relationship. When the power is turned on, the potential of the in-phase terminal is greater than the potential of the inverting terminal, and the output is a rising potential (during the power supply establishment period). The RC charging time is sufficient to delay until the power supply is stable. When the RC charging voltage is greater than 2/3Vcc, the circuit outputs "0", and the power-on reset is completed normally.

2 Using watchdog circuit to realize system protection

2.1 Reset width design requirements

Because the MCS-51 does not have a watchdog function inside (the 8096 series microcontrollers have it), this circuit needs to be expanded externally, as shown in Figure 4. The monostable circuit is a retriggerable circuit. As long as the trigger pulse (CP) is output periodically normally, the monostable will always be in the transient stage and output a low level. Through V1 clamping, the oscillation circuit stops oscillating, and the oscillator outputs "0" without affecting the RST pin. The CPU is in normal working condition. If for some reason the CP has no output, the monostable is in a steady state, and the output "1" oscillator starts oscillating, outputting a square wave to the RST pin. In order to ensure reset, the square wave width is much larger than two machine cycles, and should be at least larger than two CP cycles to ensure that the program has time to act as a watchdog.

Processing (output normal trigger pulse to stop the oscillator, output "0" does not affect the RST pin).

2.2 Periodic trigger pulse software design considerations

The software generates a periodic trigger signal to control the operation of the circuit to ensure the normal operation of the system. The following points should be noted when generating the periodic signal:

(1) The signal is not obtained by timer interrupt. This is based on the following considerations: After initialization, the timer interrupt starts working. If the main program is redirected due to some signal interference, but the timer interrupt control settings are not destroyed, the timer interrupt may work normally, and the periodic pulse may be output normally. At this time, the watchdog cannot restore the main program to normal.

(2) The Watchdog output module is placed in the main program. There should be as many Watchdog output modules as there are loops in the main program to ensure that the main program is not damaged.

(3) The working program includes the main program and the interrupt program. The watchdog not only protects the main program from flying, but also protects the interrupt program from flying. The protection process is shown in Figure 5. Set the high-level interrupt running flag to 1 and the secondary interrupt running normal flag to 2.

If the high-level interrupt cannot operate normally, there will be no flag 1. Although the secondary interrupt works normally, there will be no flag 2 because there is no flag 1. Finally, the main program has no flag 2, so the watchdog has no output, resulting in a system reset. Similarly, if the secondary interrupt cannot operate normally, flag 2 will be generated, eventually leading to a system reset; if the main program itself fails, there will be no timing output, eventually leading to a system reset, and the system will resume normal operation.

3. Repair of damaged data

The watchdog circuit can only ensure that the system can be reset after failure and resume normal operation, but this means that the previous working state has been destroyed, but it is not "freezing". The failure and transfer of the program are often caused by the destruction of the transfer flag, data or SFR control word. No matter how good the system is, it is impossible to completely avoid these damages, because various interference sources cannot be eliminated at all. In order to protect these process data from being destroyed, we can only try to make the protection as perfect as possible.

3.1 Real-time refresh of special function register (SFR) contents

Generally, the initial value of SFR has been preset in the initialization program, which represents a certain working mode. After normal operation, the content of SFR is generally unchanged. Because the content of SFR represents a specific working mode, the destruction of the content will change the originally set working mode, thus causing the system to malfunction. For example, after the system is set to work in interrupt mode, there is an interrupt return problem. The stack (SP) content has been set in the initialization program. If the SP content is changed due to some interference, the interrupt return will not be able to turn to the predetermined address, and the system will inevitably malfunction. In order to minimize the chance of damage, we put the relevant SFR in the main program Watchdog loop output module so that it can be constantly refreshed. The program diagram is as follows:

LOOP： ·

·

·

MOV SP, #10H

MOV TMOD, #12H

MOV SCON, #00H

ANL PSW, #0E7H

SETB TR0

SETB TR1

SET IT0

MOV IE, #8AH

MOV IP, #02H

·

·

·

LJMP LOOP

3.2 Nested protection of data area and bit area

Most of the unit contents in the data RAM area are key data obtained through calculations or various processing during operation. These data are more likely to be damaged. In addition to the damage caused by interference sources, calculation errors or processing errors can also cause erroneous data. For example, in order to accurately obtain the value of a receiving flag bit 01H, you must first check whether the receiving end is valid. The receiving process will determine whether it is interfered with. If it is interfered with, the flag will be refreshed (SETB 01H). If it is valid, the flag will be CLR 01H, and then enter the receiving process. The following processing is based on bit 01H. If the bit is damaged (SETB01H), the receiving process will not be able to proceed. Therefore, once it is determined to enter the receiving state, in the processing stage, it is necessary to frequently repeat the confirmation to keep the flag valid, that is, CLR01H, until the task is completed. This means that when completing a specific task, the reliability diagnosis of the relevant flags or data should be carried out as a real-time repair to minimize the possibility of damage.

4 Conclusion

There are many ways to ensure the stable operation of the system and design a system anti-interference method. We cannot be limited to conventional methods. We must take corresponding measures according to the specific conditions of the application system and the types of interference sources. The above method we have adopted has been used for several years and has been shown to be more suitable for the WCZ-X type switching system. The reliability of this product has been well verified in practical applications.

References

1 He Limin. MCS-51 series single-chip microcomputer application system design, system configuration and interface technology. Beijing: University of Aeronautics and Astronautics Press, 1990

2 Tu Shiliang, Zhang Youde, Chen Zhanglong. Single-chip microcomputer MCS-51 user manual. Shanghai: Fudan University Press, 1990