ASIC Design of SD/MMC Card Controller Based on ARM9

introduction

Nowadays, multimedia digital products are developing rapidly, and various audio and video functions are constantly enhanced, which makes the system's requirements for the performance, capacity, and security of storage media increase day by day. MMC cards and SD cards are both flash-based storage devices. In recent years, they have become the standard of the flash memory market with high storage capacity, fast data transmission rate, great mobility and higher security. They are widely used in various products such as mobile phones, MP3, MP4, and PDAs. It can be seen that it has become a universal functional interface in SOC chips for portable digital electronic products.

The SD/MMC controller designed in this paper is based on a 3G mobile phone baseband chip, whose core uses ARM926EJ, the system bus architecture is AMBA, and the controller is connected to the APB bus. By analyzing the specifications of SD cards and MMC cards, the SD/MMC card controller IP core that meets the specifications is implemented using Verilog HDL. The model of this IP is synthesized and optimized under the 0.13um standard cell process library of SMIC.

1 Working Principle of SD/MMC Card Controller

SD (Secure Digital) card and MMC (Multi Media Card) card are two common data storage cards on the market. SD card is backward compatible with MMC card.

The two have the same basic characteristics, except for some differences in data interface and transmission mode: SD card has 4 data lines, while MMC card has only 1; SD card supports security protection; while MMC card supports bit stream transmission (no limit on transmission length, that is, transmission will not stop until a stop command is received).

The controller performs a series of operations such as initialization, reading, and writing on the SD/MMC card through the SD/MMC bus. The bus includes the clock line CLK, the command line CMD, and the data line DAT3-DAT0 (MMC card has only DAT0). After power-on, the controller must transmit commands to the card according to a certain bus protocol to initialize it. There are three data formats on the bus: command packet, response packet, and data packet. Since both data and commands may go wrong during transmission, the command has a 7-bit CRC check code and the data has a 16-bit CRC check code.

When the controller reads the card, it converts the received serial data (which may be a bit stream or multiple blocks) into parallel data and stores it in the FIFO. The write operation is the same. The controller takes the parallel data out of the FIFO and sends it serially.

The working clock of SD/MMC card comes from the controller. All operations such as card commands or data transmission must be synchronized with this clock. This clock can be configured by the controller to adapt to the different clock frequencies required for normal operation of the card in different working states. It should be noted that the maximum operating frequency of SD card is 25Mhz, and the maximum operating frequency of MMC card is 20Mhz.

In short, the controller must not only output a suitable working clock, but also complete the normal operation of command/response and data reading and writing, perform CRC checks on commands and data, and generate and clear interrupts in a timely manner.

2 Controller Design and Implementation

2.1 Module Division

In the whole SOC, our TD baseband chip adopts the ARM926EJ-S core, and the system architecture is AMBA bus. In the design, the SD/MMC card controller is hung on the APB bus as the SLAVE of APB, and ARM accesses and controls the module through the APB bus. This module is mainly divided into three parts: interface module, CMD control module and DATA control module. Its structural block diagram is shown in Figure 1.

Figure 1 SD/MMC controller structure

The interface module is connected to the APB bus of ARM. Through this module, ARM can read and write the corresponding registers, thereby realizing the control of this module and the external memory card. Its read and write timing follows the APB bus read and write timing, see the literature for details.

The CMD control module mainly sends and receives signals on the CMD line. The length of the command sent by the controller to the card is fixed at 48 bits, while the length of the response received from the card is not fixed, and there are short responses (48 bits) and long responses (136 bits).

Among them, the submodule containing CRC7 requires CRC verification regardless of command or response.

The DATA control module mainly receives data through the RXDATA data line and sends data through TXDATA. There are two main data transmission modes: bit stream data transmission and multi-block data transmission. In addition, the controller also supports non-response packet data transmission. To ensure the correct transmission, a CRC16 check submodule is included.

2.2 Design of CMD control module

Since the operation commands of SD/MMC cards are inconsistent, the commands are not decoded in the module, but the command type is set by software. Single-block (signalblock data) read data command (CMD17), write data command (CMD24); multi-block (multi-block data) read data command (CMD18), write data command (CMD25), etc. require the control module to issue corresponding commands according to the content of the SD_CMD_INDEX register and make different state transitions. The state transition diagram of the CMD control module is shown in Figure 2.

Figure 2 CMD control module state transition

2.3 Design of DATA control module

The main functions of this module are to send data to the card and read data from the card. In addition, for the SD card, the module can detect whether the card is inserted through DATA[3], send a read wait signal through DATA[2], receive an interrupt signal from the card through DATA[1], and detect whether the card is busy through DATA[0].

There are some other functional modules on the APB bus, such as SPI interface controller, CAMERA controller, etc. Since they cannot occupy the bus all the time, they will not have time to process the received data or get the new sent data while reading and writing the card. Therefore, we adopt data cache and add a 64-byte FIFO.

When the controller reads the card, it needs to send the CMD9 command first to obtain the card's CSD register data, which includes the card's data length, card storage capacity, card maximum clock speed, etc. The controller can continue to read data until it sends a stop transmission command to the card; or reads a specified number of data blocks.

During the data reading process, if the card detects an error, such as out of range, address alignment error, etc., the card will stop sending data and stop in the sending-data state. The controller needs to send a stop transmission command. At this time, the card will return the error information to the controller through a response.

The controller can continue to write data to the card until it sends a stop transmission command to the card or the specified number of data blocks are written. During the data writing process, if the card detects an error, such as write protection, address out of range, address alignment error, etc., the card will stop receiving data and stop in the Receiving-data state. The controller needs to send a stop transmission command, and the card will return the error information to the controller through a response packet. After a data block is written, the card needs some time to write this data to the internal Flash. The controller needs to query the card's status and wait until the card finishes writing the data before sending the next command.

2.4 CRC Algorithm Design

CRC check is used in both CMD control module and DATA control module. CRC7 is used in CMD control module, and its formula is G(x) = x7 + x3 + 1. The logic diagram of the algorithm is shown in Figure 3.

Figure 3 CRC7 generation logic

CRC16 is used in the DATA control module, and its formula is G(x) = x16+ x12 +x5 +1. The algorithm logic diagram is the same as that of CRC7, so we will not repeat it here.

The two types of verification are essentially the same, but the latter has higher accuracy and is suitable for data transmission verification, especially long data.

3 Functional Verification and Synthesis

ModelSim software from Mentor is used for simulation. The software is licensed for use on PC, Solaris, HP-UX or Linux platforms and supports VHDL or Verilog hardware description language (HDL) simulation. It supports behavioral level simulation of all devices and VHDL or Verilog simulation stimulus.

In order to test the correctness of the design, a testbench module was written, which includes a prototype of the SD card described in HDL (so that the controller can operate the card), including generating clock signals, outputting commands, reading and writing data, generating interrupts, etc. The following is an example of testing the SDMMC read and write registers, sending commands and receiving responses, and 4-wire block data transmission:

When the chip select signal is met, the APB bus first configures the internal registers, then confirms the sending of the command, and attaches the CRC7 check code, and finally receives the response and the CRC7 check code of the response.

All transmission modes such as streaming transmission, single block, and multi-block data are simulated and synthesized using the most popular synthesis tool in the industry: DesignCompiler from SYNOPSYS. After setting the script constraints, the timing and area of ​​the controller are optimized through DC. The operating frequency meets the 125Mhz frequency of the mobile phone baseband chip (up to 200 or more), and the area is 30,000 gates, which is lower than the mainstream 40,000 gates, saving area.

Finally, the xc4vlx200-10ff1513 chip of Xilinx was used for FPGA verification. The test results show that the controller can perform data transmission to the mainstream SDMMC cards on the market and meet the requirements of the entire SOC.

4 Conclusion

After verification, the above design was packaged and manufactured using SMIC's 0.13um process library, realizing the latest SD1.0 and MMC3.31 protocols and embedding them into ASIC, making the TD terminal have external expansion storage and saving user expenses. In addition, the controller can be used as a mature IP core and transplanted into various ASIC chips based on multimedia processing, and its application is very wide.

The author's innovation: The design of this IP core provides the function of external expansion memory card for TD-SCDMA terminal baseband chips and similar handheld SOCs, and has wide and reliable portability for use in other chips.