Design of Serial Rapid10 Information Line Communication System Based on C645x

introduction

With the rapid increase in social information exchange needs and the rapid popularization of personal mobile communications, spectrum has become an increasingly valuable resource. Antenna technology uses space division multiplexing (SDMA) to distinguish signals with the same frequency and time slot by using the difference in signal propagation direction. It can expand communication capacity exponentially and combine with other multiplexing technologies to maximize the use of limited spectrum resources. In addition, in mobile communications, due to the influence of complex terrain and building structures on radio wave propagation, the mutual influence between a large number of users, delay spread, Rayleigh fading, multipath, co-channel interference, etc., seriously affects the communication quality. The use of smart antennas can effectively solve this problem.

At present, the application problem of triple play of voice, video and data is urgently needed. The core of triple play focuses on connectivity and computing power. Connectivity means that high-speed communication of data between different devices, boards and systems must be achieved; computing power means that the processors in devices, boards and systems can meet new and complex algorithm requirements. Digital signal processing (DSP) is an emerging discipline that involves many disciplines and is widely used in many fields. Since the 1960s, with the rapid development of computer and information technology, digital signal processing technology has emerged and developed rapidly. Digital signal processing is a method of processing real signals represented by digital sequences by using mathematical techniques to perform conversions or extract information. In the past two decades, digital signal processing has been widely used in fields such as communications. Semiconductor manufacturers such as Texas Instruments and Freescale have strong strength in this field.

1 Serial RapidIO and its structure

The basic specification of RapidIO interconnection technology was completed in 2001. In October 2003, the International Organization for Standardization and the International Electrotechnical Commission (IEC) unanimously adopted the RapidIO interconnection specification, namely ISO/IEC DIS 18372. At present, this technology has been implemented in system logic devices, FPGA and ASIC devices. After hard work, TI has also implemented this technology on DSP chips. The serial RapidIO interconnection architecture solves the challenges of reliability and interconnectivity in high-performance embedded systems. Embedded systems are "devices used to control, monitor, or assist the operation of equipment, machinery or plants." It can be seen that embedded systems are a combination of software and hardware, and can also cover auxiliary devices such as machinery. At present, a generally recognized definition in China is: a special-purpose computer system that is application-centric, based on computer technology, with tailorable software and hardware, and adapts to the strict requirements of application systems on functions, reliability, cost, volume, and power consumption.

The main features of DSP-based Serial RapidIO are:

①Few pins;

②Data width and speed are adjustable;

③With DMA and message passing functions;

④Support complex and adjustable topology;

⑤Support multi-point transmission;

⑥High reliability and can provide service quality assurance;

⑦Low power consumption.

The Serial RapidIO of C645x has a three-layer structure, as shown in Figure 1. The RapidIO structure mainly includes the physical layer, the transport layer, and the logical layer. The physical layer is responsible for describing the interface specifications of the device, such as packet transmission mechanism, flow control, electrical characteristics, and low-level error management; the transport layer provides routing information for transmitting packets between different endpoint devices, and the switching device works in the transport layer in a device-based routing manner; the logical layer defines the overall protocol and packet format, each packet contains a maximum of 256 bytes of payload, and transactions access the address space through Load, Store, or DMA operations. In Figure 1, the logical layer includes the I/O system, transmission messages, global shared memory, and expansion units reserved for future possible functional additions.

2 System Hardware Structure

The TMS320C645x series DSP is a 1.2 GHz DSP launched by TI. It is mainly used in telecommunications, medical electronics and emerging electronics industries. It can connect to 32-bit DDR2 memory and 66 MHz PCI interface. It has 2 serial Gigabit media independent interfaces, Ethernet MAC port, 1 Gigabit Ethernet gateway, and a telecommunications serial interface for seamless connection of public telecommunications data streams. These features of TMS320C645x are very suitable for ultra-high-speed data processing systems. In high-speed data systems, the transmission of large amounts of data between chips is very critical. Only by quickly and timely sending or reading data can the system's pressure on data storage be reduced. Figure 2 is a block diagram of the internal structure of the serial RapidIO of the TMS320C645x series DSP.

As can be seen from Figure 2, the received differential data enters the serial RapidIO. First, the RapidIO module detects the data transmission clock frequency according to the rising edge change speed of the data, and receives the following data at this frequency. Then, the received serial data is converted into 10-bit parallel data through the S2P (Series to Parallel) unit, thereby reducing the data transmission speed by 10 times. After the physical layer obtains the parallel data, it sends the data to the logic layer, which is sequentially processed through decoding, FIFO, CRC check and unpacking, sent to the buffer and processed, and finally sent to the DSP processing unit through the DMA bus to complete the data reception.

The RapidIO connection between two DSPs is simple and convenient. As shown in Figure 3, you only need to connect the data transmission and reception accordingly. Since RapidIO has four parallel data buses, if all data buses are connected, the highest communication rate can be ensured. You can also use one data bus for communication, in which case the data transmission speed is reduced to 1/4 of the highest communication rate. If multiple DSPs need to communicate with each other, a single data communication method is generally used. The three DSPs in Figure 4 communicate with each other using the RapidIO bus. In addition, the data ground and analog ground between the DSPs need to be connected separately (see Figure 3).

3 System Software Design

There are three steps to setting up the RapidIO bus:

① Set the RapidIO clock and set the data transmission and reception rate through the SERDES_CFG_CNTL register;

② Enable the RapidIO receiver and set some parameters related to data reception, including adaptive equalization design of differential signals, phase deviation setting, signal loss setting, etc.;

③ Enable the RapidIO transmitter and set some parameters related to data transmission, including transmission rate, bus width, etc.

The code to set the RapidIO rate to 3.125 Gbps and enable the receiver and transmitter is as follows:

The start and end are initiated and controlled by the host, and the slave passively receives commands and executes instructions. When the slave needs to actively send data to the host, it can only send an interrupt to the host; after the host responds to the interrupt, it sends a data read command. The specific workflow is shown in Figure 5. The command initiator of the host sends an operation command and transmits the send request packet to the command execution mechanism of the slave through the command transmission mechanism. The command execution mechanism of the slave may perform data reception (the host sends data to the slave) and data transmission (the host requires the slave to send data) tasks. The command execution mechanism completes the corresponding command and sends a response packet to the host. The host determines that the command is completed, clears the command status, and completes the operation of the entire command.

RapidIO may generate errors during data transmission. According to the error conditions, RapidIO sends two different interrupts to the CPU: status error, in which case the CPU should reset or resynchronize RapidIO; and severe error, in which case the CPU should reset all devices related to RapidIO.

4 Conclusion

This article introduces the serial RapidIO bus in DSP, details the hierarchy and internal structure of the bus, and introduces the hardware and software system design in combination with RapidIO communication between multiple DSPs. The bus can achieve 10 Gbps high-speed data communication, which can meet the needs of various communication services such as voice, image and data. The entire communication system has simple connection, reliable communication and strong practicality.