Reconfigurable Circuit PLD Based on SRAM

The emergence of reconfigurable PLD (programmable logic device) based on SRAM has created conditions for system designers to dynamically change the logical functions of PLD in the running circuit. PLD uses SRAM cells to store word configuration data, which determines the internal interconnection and function of PLD. Changing this data also changes the logical function of the device. Since SRAM data is volatile, this data must be stored in non-volatile memory such as EPROM, EEPROM or FLASH ROM outside the PLD device so that the system can download it to the PLD at the appropriate time, thereby realizing in-circuit reconfigurability ICR (In-Circuit Reconfigurability).

How to implement ICR? ALTER company's application solution AN88 introduces in detail an ISP&ICR design method based on the DS87C520 microcontroller, and puts its source code on the ALTERA website for users to download for free. When designing an electronic device that requires an ICR function, after a detailed analysis of the method introduced in AN88, the author found that the circuit structure introduced in the application solution is complex, and the requirements and cost for the microcontroller performance and microcontroller development device are high, and it is only suitable for PLD circuits with an operating voltage of 5V. This article introduces the PLD ICR control circuit designed by the author. Compared with the method introduced by ALTERA, it not only has a simple circuit structure, easy development, small size, and low cost, but also can achieve in-circuit reconfiguration of PLD devices with an operating voltage of 3.3V or 5V by simply changing the power supply voltage of the ICR control circuit.

ICR control circuit hardware principle

The schematic diagram of the ICR control circuit is shown in Figure 1. U1 in the figure is the core device of the ICR control circuit. It is a 20-pin low-cost microcontroller P87LPC762 launched by PHILIPS at the end of 1999. The microcontroller has 2K bytes of program memory, 128 bytes of RAM, 18/15 I/Os, WATCHDOG, a universal serial interface UART and a hardware I2C bus controller. P87LPC762 uses the 80C51 accelerated processor structure. Its instructions are compatible with 80C51, but the execution speed of instructions is twice that of the standard 80C51 microcontroller at the same clock. Because it uses a hardware I2C bus controller, it saves a lot of software and hardware resources. U2 and U3 are serial EEPROM AT24C256 from ATMEL, whose serial communication protocol is I2C and has a capacity of 32K bytes. In the circuit, U2 and U3 are used to store the configuration data of PLD.

The working process of the ICR control circuit is as follows: the PLD configuration file compiled and produced by MAXPLUS Ⅱ is pre-processed, downloaded to U1 through the serial communication port of the PC, and stored in EEPROM U2 and U3 under the control of U1. U1 then downloads the PLD configuration data stored in U2 and U3 to the PLD in the circuit through five I/O ports such as P0.2, P0.3, P0.4, P0.6 and P0.7 according to the system requirements.

Because the PLD in the author's circuit design is EP1K30 of ACEX series of ALTERA, and the capacity of its configuration file is 52K bytes, two AT24C256 are used in the circuit to store the configuration data of PLD. If the configured PLD is EPF10K10 or EPF10K20, only one AT24C256 is needed. At this time, the entire ICR control circuit has only two ICs, which can be said to be the simplest and lowest cost ICR control circuit at present. When applying this circuit, readers can use 1 to 4 AT24C256 according to the size of its PLD file (the size of the PLD configuration file can refer to the application solution AN116 of ALTERA).

Key points of ICR control circuit software design

In the ICR control circuit introduced in Figure 1, the EEPROM AT24C256 that stores the PLD configuration data uses the I2C serial bus for data exchange, and its data exchange speed is slow (when the operating voltage is 5V, its maximum I2C bus clock is 1MHz), and the PLD configuration data is relatively large, usually more than tens of K bytes. Therefore, how to improve the configuration speed of the ICR control circuit introduced in Figure 1 will be a key point in software design.

The PLD devices with ICR function produced by ALTERA include FLEX6000, FLEX10K, APEX and ACEX series. Their configuration methods can be divided into four methods: PS (passive serial), PPS (passive parallel synchronous), PSA (passive parallel asynchronous), PSA (passive serial asynchronous) and JTAG (Joint Test Action). Among these four methods, PS method is the most widely used because the interconnection between PLD and configuration circuit is the simplest and there is no limit on the minimum frequency of configuration clock. Therefore, PS configuration method is also used in the ICR control circuit introduced in Figure 1 to realize ICR function. Figure 2 is the timing diagram of PS configuration method.

When reading data from AT24C256, there are three ways: reading the current address, random reading, and sequential reading. Among these three ways, sequential reading is the simplest and fastest, because in the same AT24C256, only one read command needs to be written to sequentially read all the data in the entire AT24C256 starting from address 0. The timing diagram of AT24C256 sequential reading is shown in Figure 3.

Comparing Figure 2 and Figure 3, it can be seen that the PS configuration timing diagram of the PLD and the AT24C256 sequential read timing diagram have many similarities. The only difference is that in the PS configuration mode, the data configuration order is that the lowest bit of the sequence is input first, while the I2C bus read process is that the highest bit of the sequence is output first. The input and output order between them is just the opposite. If the configuration file of the PLD is preprocessed to store the lowest bit of its configuration data in the highest bit of the EEPROM, then during the configuration process, the current bit data read from the EEPROM I2C bus is exactly the current bit that needs to be input into the PLD during the PS configuration. This will be the most effective measure to increase the configuration speed of the ICR and shorten the configuration time. The specific process is as follows:

After the PLD program designed by the user is compiled by MAXPLUS Ⅱ, a SRAM target file with the suffix .sof will be generated. This file contains control characters other than configuration data and cannot be directly written into the PLD. It is necessary to use the programming file conversion function of MAXPLUS Ⅱ to generate a tabular text file with the suffix .ttf. This file is a PLD configuration file without any additional symbols and can be directly configured into the PLD. Before downloading each byte in this file to the EEPROM of the ICR control circuit, D7 D6 D5 D4 D3 D2 D1 D0 is converted to D0 D1 D3 D4 D5 D6 D7 and then written into the EEPROM. In the PLD configuration process, its configuration data is not processed in any way, and the current bit data read from the EEPROM is the current bit data that needs to be configured into the PLD at this time (this is why the author uses the I2C EEPROM with a slower clock frequency, instead of the SPI interface EEPROM with a relatively fast clock frequency but no sequential read function), thereby achieving the purpose of shortening the configuration time of the ICR control circuit.

in conclusion

This article introduces a PLD ICR control circuit based on a microcontroller. The control circuit has a simple structure, small footprint, and high cost performance. It is suitable for electronic devices that require ICR functions. The ICR control circuit is designed for configuring the ALTERR series PLD devices, and with a little modification, it is also suitable for XILINX's FPGA devices. The main weakness of this configuration circuit is that the configuration rate is slow, and it can only be used for applications that do not require high configuration rates.

Note: One of the concepts in this article is ICR (In-Circuit Reconfigurability), which is a concept proposed by ALTERA. It is a concept that is parallel to the current ISP (In System Programmabled) and has a similar meaning to IAP (In Application re-Programmable). However, the author uses ALTERA's PLD, so the concept of ICR is used in this article.