The extended design of DPTR in 8051 single chip microcomputer

Abstract Firstly, the difference in data transfer execution efficiency between the traditional 8051 microcontroller and the 8051 microcontroller after DPTR extension is compared and analyzed when performing large-scale data transfer. By analyzing the factors involved in DPTR operation in detail, the expansion of DPTR is specifically implemented, and actual simulation tests are carried out.

Keywords 8051 MCU DPTR data transfer execution efficiency

The emergence of single-chip microcomputers is a milestone in the history of computer technology development. It has enabled computers to move from massive numerical calculations to the control field. Among single-chip microcomputers, the 8051 series is the most classic and is still the most popular and widely used 8-bit MCU architecture. Many technicians in the industry have continuously expanded the performance of the 8051 series chips, making them continuously improved, thus forming a huge system. In the traditional 8051 series single-chip microcomputers, a set of two-byte registers (data pointer DPTR) is set up to access the external 64 KB data memory and I/O interface circuits; but in today's 8051 single-chip microcomputer applications, especially in embedded systems, large-scale data transfer operations are often involved, and the use of a set of data pointers in the traditional 8051 is stretched. Therefore, if the data pointer is designed as two or more groups in the 8051 design, it will be quite simple and fast when performing large-scale data transfer operations. In this context, this paper first analyzes the significance of DPTR expansion based on the data transfer execution efficiency, and implements DPTR expansion on the MCS8051 core of Oregano [1].

1 DPTR extended meaning

To illustrate the significance of the DPTR extension in the 8051, we compared the implementation of large-scale data transfers before and after the DPTR extension. To make the comparison clearer, the concept of data transfer execution efficiency is proposed.

The data transfer execution efficiency v is defined as the number of machine cycles consumed to transfer a single byte of data, that is, v=nt. Among them, n represents the number of bytes of data transferred; t represents the machine cycles consumed, and its unit can be set to byte/machine cycle.

In 8051 without DPTR extension, large-scale data transfer can be achieved by setting the address buffer. The specific routine is as follows:

MOVPRE:
MOV50H, #s_adrh
MOV51H, #s_adrl
MOV52H, #t_adrh
MOV53H, #t_adrl
MOVR2, #64
REMOVE:MOV DPH, 50H
MOV DPL, 51H
MOVX A, @DPTR
INC DPTR
MOV 50H, DPH
MOV 51H, DPL
MOV DPH, 52H
MOV DPL, 53H
MOVX @DPTR,A
INC DPTR
MOV 52H, DPH
MOV 53H, DPL
DJNZ R2, REMOVE

In this example, 50H and 51H are used to store the data source address s_adr (s_adrh is the high byte, s_adrl is the low byte), and 52H and 53H are used to store the data destination address t_adr (t_adrh is the high byte, t_adrl is the low byte), so as to transfer the 64 bytes of data starting from the source address to the destination address. In 8051, it takes (14+28×n+2) machine cycles to perform an n-byte data shift operation, and the data transfer execution efficiency is v=n/(14+28×n+2). In this example, n is 64, and it is calculated that a total of 1,808 machine cycles are required, and the execution efficiency v is about 0.035 4 bytes/machine cycle, and in this implementation method, 4 on-chip memory (RAM) units of 8051 are required.

For example, 8051 has two sets of DPTR, and DPTR selection can be realized through special instructions. The SETDPTR0 instruction can be set to select DPTR0, the SETDPTR1 instruction can be set to select DPTR1, #s_adr represents the data source address, and #t_adr represents the data destination address. Then the program can be designed as follows:

MOVPRE:
SETDPTR0
MOVDPTR,#s_adr
SETDPTR1
MOV DPTR,#t_adr
MOV R2,#64
REMOVE2:
SETDPTR0
MOVX A,@DPTR
INC DPTR
SETDPTR1
MOVX @DPTR,A
INC DPTR
DJNZ R2,REMOVE2

In the program, for the special instructions SETDPTR0 and SETDPTR1, the DPTR selection can be realized by setting the special function register (SFR) to indicate the DPTR status and operating the SFR. Therefore, the DPTR selection instruction can be implemented by a 3-byte instruction. In the case of two sets of DPTR, it takes (14+12×n+2) machine cycles to execute large-scale data transfer, and the data transfer execution efficiency is v=n/(14+12×n+2). In this routine, it takes 784 machine cycles to execute 64-byte data transfer, and the execution efficiency is about 0.085 64 bytes/machine cycle.

Through the above comparison, it is found that the data transfer execution efficiency ratio of the 8051 with two sets of DPTRs is (14+28×n+2)/(14+12×n+2) when transferring large amounts of data compared to the traditional 8051. As shown in Figure 1, as the amount of data transferred increases, that is, as the value of n increases, the execution efficiency ratio also increases, and finally approaches 2.33.

Figure 1 Comparison of data transfer execution efficiency

The above analysis shows that setting two sets of DPTR in 8051 will greatly improve the efficiency of data transfer execution. Considering the resource occupation, using the extended DPTR method to realize data transfer only requires adding an SFR in 8051. Therefore, implementing DPTR extension in 8051 can significantly speed up the data transfer rate under the condition of low resource occupation. This is of great significance for large-scale data transfer in embedded system applications.

2 Specific design and implementation

To expand DPTR in 8051, we first need to analyze the related instructions of DPTR, and then determine which instruction operations will be affected by expanding it; and according to the instructions involved, analyze the corresponding modules, and finally make design modifications to each module.

2.1 Analysis of related instructions

Among the 111 instructions in the 8051 standard instruction set, there are five types of instructions related to DPTR, namely:

① Program memory table lookup instruction, "MOVC A, @A + DPTR";
② External RAM transfer instruction, "MOVX A, @DPTR" and "MOVX @ DPTR , A";
③ Register data transfer instruction, that is, read and write operations on DPTR. In 8051, DPTR is composed of DPH (DPTR high 8-bit byte) and DPL (DPTR low 8-bit byte), and DPH and DPL, like general SFRs, can be used as registers for read, write, and stack operations;
④ Program transfer instruction, "JMP @A + DPTR";
⑤ Operation instructions, which can perform operation operations on DPH and DPL respectively.

Through the analysis of the above five types of instructions related to DPTR, we can know that the third and fifth types of instructions operate DPTR as SFR. The first and fourth types of instructions are data transfer operations between DPTR and PC pointer; the second type of instructions are data transfer operations on the off-chip RAM address register. Therefore, the operation of DPTR specifically involves the following three modules in 8051: SFR read and write module, PC pointer module and off-chip RAM address module, so the expansion of DPTR is also carried out in these three modules.

2.2 Specific module design

The DPTR status register can be set to dptr_sel, and the DPTR selection can be realized by operating the DPTR status flag dps. When dps = 0, DPTR0 is selected; when dps = 1, DPTR1 is selected. In 8051, DPTR is composed of DPH and DPL respectively, so the selection of DPTR is actually the selection of special function registers DPH0, DPL0 and DPH1, DPL1.

Based on the above design ideas, the author has made corresponding modifications in the three modules involved in DPTR operation.The MCS8051 core selected in this design is designed with VHDL language and is fully compatible with the standard 8051 instruction set.

In the SFR read and write module, the read and write modules should be modified separately. By analyzing the MCS8051 design code, it can be known that the read operation of DPTR is realized by transferring the data in DPTR to the data temporary storage register S_REGDATA and then reading S_REGDATA. Therefore, the selection bit dps can be used to select DPTR before temporary storage of DPTR data. The specific diagram is shown in Figure 2.

When writing to DPTR, it is actually operating on DPH and DPL (DPH address is 83H, DPL address is 82H), so when writing to DPTR, it is necessary to operate DPH and DPL separately. In MCS8051, the write operation to SFR is actually to temporarily store the data to be written in the S_DATA register first, and then write the S_DATA data to DPH and DPL respectively. Therefore, before writing the S_DATA data, DPTR0 and DPTR1 can be selected and judged to implement the write operation to DPTR0 and DPTR1, that is, when dps=1, S_DATA data is written to DPH1 and DPL1; when dps=0, S_DATA data is written to DPH0 and DPL0. The specific structure is shown in Figure 3.

Figure 2 Schematic diagram of DPTR read moduleFigure 3 Structure diagram of DPTR write module

In the PC pointer module and the off-chip RAM address module, since the DPTR read operation is also involved, the modification of this module is similar to that in the SFR read module, and dps is also used to implement the selection of DPTR0 and DPTR1.

3 Simulation Test

In MCS8051, modifications were made to the above three modules, DPTR was expanded into two groups, and DPTR0 and DPTR1 were selected by operating the DPTR status flag dps in DPTR_SEL (set to SFR E1H), and simulation tests were performed using the simulation software Modelsim6.0. Since the three modules, SFR read-write module, PC pointer module and off-chip RAM address module, were modified when implementing DPTR expansion, the simulation test of DPTR expansion was also divided into three modules.

3.1 Test for SFR read and write module

The test of this module is mainly to test the data transmission of DPTR0 and DPTR1. First, operate the DPTR status flag dps bit, select DPTR0 and DPTR1 respectively; then write them respectively; finally, output the data values ​​in DPTR0 and DPTR1 to register A in sequence. The specific waveform is shown in Figure 4.

Figure 4 SFR read and write test waveform

As shown in Figure 4, before and after the execution of instruction 75E100 (i.e., resetting dps and selecting DPTR0), the values ​​output by DPH and DPL (executing instructions E583, E582) to register A are different. Before the execution of instruction 75E100, the output of DPH is 55 and the output of DPL is 66. After the execution, the outputs are 11 and 22 respectively, which indicates that the DPTR selection is performed through dps, and the read and write operations are correct, that is, the modification of the SFR read and write module is correct.

3.2 Data lookup table test for PC pointer

For this module, a table lookup test was performed, that is, the addresses of the two data tables data1 and data2 were written into DPTR0 and DPTR1 respectively; then DPTR0 and DPTR1 were selected by DPS, and the data table lookup and output were performed on them respectively. The specific waveform is shown in Figure 5.

Figure 5 PC pointer data table lookup waveform

After selecting DPTR1 (data2 address has been stored, execute instruction 75E180), clear register A (execute instruction 7400), and output the table lookup data (execute instruction 93), the output data is 11H; then select DPTR0, clear register A again, and perform table lookup output, the output data is 44H. By comparison, it can be found that the output data is consistent with the data in the table. This shows that the data lookup operation is correct by selecting DPTR0 and DPTR1 through dps, that is, the modification of the PC pointer module is correct.

3.3 Off-chip RAM data read and write test

For the off-chip RAM data read and write test, that is, large-scale data transfer, the test plan is: first write addresses adr0 and adr1 into DPTR0 and DPTR1 respectively, then write data to these two addresses respectively, and finally read the data of these two addresses through DPTR0 and DPTR1, and compare the read result with the write result. The specific test waveform is shown in Figure 6.

Figure 6 Off-chip RAM data read and write waveform

After setting dps (executing instruction 75E180) and selecting DPTR1, the adr1 data in the off-chip RAM is read out, and the output data is 77H; after resetting dps (executing instruction 75E100) and selecting DPTR0, the adr0 data is read out, and the output data is 44H. By comparison, it can be found that it is consistent with the written data. This shows that the data reading and writing of the off-chip RAM by selecting DPTR0 and DPTR1 through dps is correct, which means that the modification of the off-chip RAM address module is correct.

3.4 FPGA simulation test

Based on the 8051 microcontroller MCS8051, we also conducted actual FPGA simulation tests. First, using the RS232 interface, we received large amounts of data from the computer and wrote them to the adr0 address of the MCS8051 off-chip RAM; then, using the method given in Example 2, we transferred large amounts of data and wrote the data to adr1; finally, we sent the data in adr1 to the computer through the RS232 interface. By comparing the sent and received data, we found that the author's expansion of DPTR was correct.

Conclusion

By extending DPTR, the execution efficiency of 8051 in large-scale data transfer can be greatly improved, which makes the embedded system using extended 8051 as microcontroller greatly improve its processing speed in large-scale data transfer. The method described in this article can also be used to expand DPTR into multiple groups, but its specific application significance needs further discussion.