Analysis of MCU Hardware Parameter Design

Abstract: With the emergence of new technologies and processes, the application of high-speed microcontrollers is becoming more and more extensive, and higher requirements are put forward for the reliability of hardware. This article will describe the key points of high-speed microcontroller design from the perspective of hardware reliability.
Keywords: high-speed microcontroller reliability characteristic impedance SI PI EMC thermal design
Introduction
With the continuous improvement of the frequency and integration of microcontrollers, the power per unit area and the speed of digital signals, while the amplitude of signals is constantly decreasing, the originally designed and stable microcontroller system may now have inexplicable errors. After analyzing the reasons, no problem can be found. In addition, due to market demand, products need to be implemented with high-speed microcontrollers. How can designers quickly master high-speed design?
Hardware design includes logic design and reliability design. Logic design implements functions. Hardware design engineers can directly determine whether the requirements are met by verifying whether the functions are implemented. There is a lot of information in this regard, so I will not describe it here. Hardware reliability design is mainly reflected in key parameters such as electrical and thermal. I summarize these into five parts: characteristic impedance, SI, PI, EMC, and thermal design.
1 Characteristic impedance
In recent years, with the increasing speed of digital signals, electromagnetic waves and related square wave propagation issues should also be considered when wiring printed circuit boards. In this way, the original simple wires have gradually transformed into complex transmission lines of high frequency and high speed.
Under high frequency conditions, the copper wires that transmit signals on printed circuit boards (PCBs) can be regarded as a conductive line composed of a series of equivalent resistors and a parallel inductor, as shown in Figure 1. Considering only the effects of stray distributed series inductance and parallel capacitance, the following formula is obtained:
Where Z0 is the characteristic impedance, in Ω.
The characteristic impedance Z0 of the PCB is closely related to the layout and routing method in the PCB design. The factors that affect the characteristic impedance of the PCB routing are mainly: the width and thickness of the copper wire, the dielectric constant and thickness of the medium, the thickness of the pad, the path of the ground wire, the surrounding routing, etc.
In the characteristic impedance design of the PCB, the microstrip line structure is the most popular and therefore has been the most widely promoted and applied. There are four most commonly used microstrip line structures: surface microstrip, embedded microstrip, stripline, and dual-stripline. The following only describes the surface microstrip line structure, and other types can refer to relevant materials. The surface microstrip line model structure is shown in Figure 2. The
calculation formula of Z0 is as follows:
For differential signals, the correction formula for its characteristic impedance Zdiff is as follows:
In the formula:
——The dielectric constant of the PCB substrate;
b——The width of the PCB transmission wire;
d1——The thickness of the PCB transmission wire;
d2——The thickness of the PCB dielectric layer;
D——The line distance between the edges of the differential line pairs.
It can be seen from the formula that the characteristic impedance is mainly determined by, b, d1, and d2. By controlling the above four parameters, the corresponding characteristic impedance can be obtained.

2 Signal Integrity (SI)
SI refers to the ability of a signal to respond with the correct timing and voltage in a circuit. If the signal in the circuit can reach the IC with the required timing, duration and voltage amplitude, the circuit has good signal integrity. On the contrary, when the signal cannot respond normally, a signal integrity problem occurs. Broadly speaking, signal integrity problems are mainly manifested in five aspects: delay, reflection, crosstalk, synchronous switching noise and electromagnetic compatibility.
Delay refers to the transmission of the signal at a limited speed on the wire of the PCB board. There is a transmission delay between the signal from the transmitter to the receiver. The delay of the signal will affect the timing of the system. In high-speed digital systems, the transmission delay mainly depends on the length of the wire and the dielectric constant of the medium around the wire. When the
characteristic impedance of the wire on the PCB board (called a transmission line in a high-speed digital system) does not match the load impedance, a part of the energy of the signal will be reflected back along the transmission line after it reaches the receiving end, causing the signal waveform to be distorted, and even signal overshoot and undershoot. If the signal is reflected back and forth on the transmission line, ringing and surround oscillation will occur.
Since there is mutual capacitance and mutual inductance between any two devices or wires on the PCB, when the signal on a device or a wire changes, its change will affect other devices or wires through mutual capacitance and mutual inductance, which is crosstalk. The intensity of crosstalk depends on the geometric size and mutual distance of the devices and wires.

Signal quality is manifested in several aspects. We will not introduce the well-known frequency, period, duty cycle, overshoot, ringing, rise time, fall time, etc. in detail here. The following mainly introduces several important concepts.
① High time refers to the time that is higher than Vih_min in a positive pulse.
② Low time refers to the time that is lower than Vil_max in a negative pulse, as shown in Figure 3.
③ Setup time refers to the minimum time that an input signal must remain stable before the reference signal reaches the specified transition.
④ Hold time is the minimum time that data must be stable after the specified transition at the reference pin, as shown in Figure 4.
⑤ Setup time margin refers to the difference between the setup time of the designed system and the minimum setup time required by the receiving chip.
⑥ Hold time margin refers to the difference between the hold time of the designed system and the minimum hold time required by the receiving chip.
⑦ Clock skew refers to the time difference between different receiving devices receiving the same clock drive output.
⑧Tco (time clock to output) is a parameter that defines all device delays, that is, Tco = internal logic delay + buffer delay.
⑨The maximum elapsed time (Tflightmax), that is, the final switch delay, refers to the time to reach the high threshold voltage on the rising edge and maintain the high level, minus the buffer delay required for driving.
⑩The minimum elapsed time (Tflightmin), that is, the first settle delay, refers to the time to reach the low threshold voltage on the rising edge, minus the buffer delay required for driving.
Clock jitter is caused by the instability jitter between each clock cycle. It is generally caused by the instability of the PLL when driving the clock. At the same time, the clock jitter causes the effective clock cycle to decrease.
Crosstalk. When the current on one of the two adjacent signal lines changes (called the aggressor), the current on the other signal line will also change due to the influence of the induced current (called the victim).
SI is a system problem and must be viewed from a system perspective. The following is a breakdown of the problem.
◆ Transmission line effect analysis: impedance, loss, backflow...
◆ Reflection analysis: overshoot, ringing...
◆ Timing analysis: delay, jitter, SKEW...
◆ Crosstalk analysis
◆ Noise analysis: SSN, ground bounce, power sag...
◆ PI design: determine how to select capacitors, how to place capacitors, and the appropriate PCB stacking method...
◆ Analysis of the influence of parasitic parameters of PCB and devices
◆ Termination technology, etc.
3 Power integrity PI
The proposal of PI stems from the huge error caused by SI analysis based on wiring and device models without considering the influence of power supply. The relevant concepts are as follows.
◆ Electronic noise refers to the random fluctuations of electrical signals generated by certain components in electronic circuits.
◆ Ground bounce noise. When many digital signals on the PCB board are switched synchronously (such as the data bus and address bus of the CPU), due to the impedance on the power line and the ground line, synchronous switching noise will be generated, and ground plane bounce noise (referred to as ground bounce) will also appear on the ground line. The strength of SSN and ground bounce also depends on the I/O characteristics of the integrated circuit, the impedance of the power layer and ground plane layer of the PCB board, and the layout and wiring method of high-speed devices on the PCB board. The increase of load capacitance, the decrease of load resistance, the increase of ground inductance, and the increase of the number of switching devices will all lead to the increase of ground bounce.
◆ Backflow noise. Only when the loop is formed can the current flow and the entire circuit can work. In this way, the current on each signal line must find a path to return from the end to the source. Generally, a plane close to it is selected. Due to the division of the ground plane (including power and ground), for example, the ground layer is divided into digital ground, analog ground, shielding ground, etc., when the digital signal reaches the analog ground area, ground plane backflow noise will be generated.
◆ Breakpoint is the point where the impedance of the signal line suddenly changes. If a via is used to transmit the signal to the other side of the board, the vertical metal part between the boards is an uncontrollable impedance. The more such parts, the greater the total amount of uncontrollable impedance on the line. This will increase reflection. In addition, the 90° turning point from horizontal to vertical is a breakpoint, which will produce reflection. If such vias cannot be avoided, then try to reduce their appearance.
To a certain extent, we can only reduce the series of adverse results caused by incomplete power supply, generally starting from reducing the series winding of signal lines, adding decoupling capacitors, and providing a complete ground layer as much as possible.
4 EMC
EMC includes two parts: electromagnetic interference and electromagnetic anti-interference.
Generally, digital circuits have strong EMS capabilities, but large EMI. The control interference of electromagnetic compatibility technology adopts the strategy of active prevention, overall planning, and the combination of "confrontation" and "guidance". The
main EMC design rules are:
① 20H rule. The edge of the PowerPlane (power plane) board is less than 20 times the distance between it and the GroundPlane (ground plane).
② Ground plane processing. The ground plane has the function of an image plane (ImagePlane) in electromagnetics. If the signal line is parallel and adjacent to the ground plane, an image current can be generated to offset the radiation field caused by the signal current. The signal line on the PCB will form a Micro-strip Line or Strip Line structure commonly seen in microwave engineering with the adjacent ground plane. The electromagnetic field will be concentrated in the dielectric layer of the PCB to reduce electromagnetic radiation.
Because the EMI performance of the Strip Line is better than that of the Micro-strip Line. Therefore, some routing lines with large radiation, such as clock lines, are best routed into a Strip Line structure. ③ Partition design of mixed signal PCB. The first principle is to minimize the area of ​​the current loop as much as possible; the second principle is that the system only uses one reference plane. On the contrary, if there are two reference planes in the system, a dipole antenna may be formed; and if the signal cannot return through the smallest possible loop, a large loop antenna may be formed. For situations where it is really necessary to cross zones, it is necessary to add high-frequency capacitors between the two zones.
④ Control EMI radiation through PCB layered stacking design. The role and design techniques of PCB layered stacking in controlling EMI radiation can also reduce EMI through appropriate stacking.
From the perspective of signal routing, a good layering strategy should be to place all signal routing in one or several layers, which are close to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the "layering" strategy.
⑤ Chassis design to reduce EMI. Due to the requirements of manufacturing, assembly, maintenance, heat dissipation and observation, the actual chassis shielding body generally has holes of different shapes and sizes. Measures must be taken to suppress the electromagnetic leakage of the holes. Generally speaking, the size of the hole leakage depends mainly on the area of ​​the hole, the maximum linear dimension on the hole cross section, the frequency and the depth of the hole.
⑥ Other technologies. Reasonably placing capacitors of appropriate capacity near the power pins of the IC can make the jump of the IC output voltage faster. However, the problem does not end there. Due to the limited frequency response characteristics of the capacitor, it is impossible for the capacitor to generate the harmonic power required to drive the IC output cleanly over the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop across the inductor of the decoupling path. These transient voltages are the main source of common-mode EMI interference. In order to control common-mode EMI, the power layer must help decoupling and have a sufficiently low inductance. This power layer must be a well-designed pair of power layers. The answer to the question depends on the power layering, the material between the layers, and the operating frequency (i.e., the function of the IC rise time). Usually, the spacing of the power layer is 0.5mm (6mil), and the interlayer is FR4 material, then the equivalent capacitance of each square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.
5 Thermal design
The density of electronic components is much higher than before, and the power density has also increased accordingly. Since the performance of electronic components changes with temperature, the higher the temperature, the lower their electrical performance.
(1) Principle of heat dissipation of digital circuits
The heat generated by semiconductor devices comes from the power consumption of the chip. The accumulation of heat will inevitably lead to an increase in the temperature of the semiconductor node. As the node temperature increases, the performance of semiconductor devices will decrease, so chip manufacturers have specified the node temperature of semiconductor devices. In high-speed circuits, the power consumption of the chip is relatively large. Under normal conditions, heat dissipation cannot ensure that the junction temperature of the chip does not exceed the allowable operating temperature. Therefore, the heat dissipation of the chip needs to be considered.
Under normal conditions, heat is transferred through three methods: conduction, convection, and radiation.
Three heat transfer methods need to be considered when dissipating heat. For example, materials with good thermal conductivity, such as copper, aluminum and their alloys, are used as thermal conductive materials, convection is enhanced by adding fans, and radiation capacity is enhanced by material processing. Simple heat
transfer model: A thermal resistance parameter is introduced in thermal analysis, which is similar to the resistor in the circuit. If the resistance calculation formula in the circuit is R=ΔE/I, the corresponding thermal resistance corresponding formula is R=Δt/P (P represents power consumption, unit W; Δt represents temperature difference, unit ℃). The unit of thermal resistance is ℃/W, which represents the temperature rise caused by a 1W increase in power. Considering the heat transfer of the integrated chip, the temperature calculation model described in Figure 5 can be used.
From the above, it can be deduced that
Tc=Tj-P×RJC
, that is, when the measured value of Tc is less than the maximum value calculated based on the data provided in the data sheet, the chip can work normally.
(2) Heat dissipation
In order to ensure that the chip can work properly, Tj must not exceed the allowable temperature provided by the chip manufacturer. According to Tj=Ta+P×R, if the ambient temperature is reduced, or the power consumption is reduced, the thermal resistance is reduced, etc., Tj can be reduced. In actual use, the requirements for ambient temperature may be more stringent, and the power consumption can only be reduced by relying on the chip manufacturer's technology. Therefore, in order to ensure the normal operation of the chip, designers can only consider reducing thermal resistance.
Conclusion
The high-speed microcontroller design ideas and methods mentioned above have been practiced and developed in foreign companies, but there is still little research and practice in this area in China. This design idea has been practiced and explored in our company, which has improved product reliability. I recommend it to all colleagues here and hope to discuss it together.