Interface between MAX121 and TMS320VC5402 in high-speed data acquisition

TMS320VC5402 is TI's fifth-generation DSP, a low-power DSP chip specifically based on digital signal processing, with an operating frequency of up to 10ns, and is widely used in digital signal processing. The chip provides 2 MCBSPs, which can work in both SPI mode and universal serial port mode, and is flexible in system design. MAX121 is a 14-bit analog/digital converter with on-chip T/H, low drift, low noise, low power consumption and fast conversion with a dedicated DSP launched by MAXIM. It only consumes 210mW, has a conversion time of 2.9 s, and a SIND of 78dB. It can be connected to the TMS320 series DSP, ADSP series and Motorola series, and has a simple design.

MAX121 chip introduction

MAX121 functional block diagram

Figure 1 Functional Block Diagram The functional block diagram of the MAX121 chip is shown in Figure 1. It has 16-pin and 20-pin models, the 16-pin has DIP and SO packages, and the 20-pin has SSOP packages.

Figure 2 and Figure 3

MAX121 operating parameters

VDD to DGND 0.3 ~ +6V; VSS to DGND +0.3 ~ 7V;

AIN to AGND 15V; AGND to DGND 0.3V;

digital input to DGND (CS, CONVST, MODE, CLKIN, INVCLK, INVFRM) -0.3 (Vdd + 0.3V);

digital output to DGND (SFRM, FSTRT, SCLK, SDATA) +0.3 (Vdd + 0.3V); Strength exceeding the above extreme parameters may cause permanent damage to the device. These parameters are only extreme parameters and do not mean that the device can work effectively under extreme parameter conditions or any other working conditions beyond the technical specifications.

The working principle of MAX121 is shown in Figure 2. When the conversion starts, the buffer is disconnected from the AIN terminal and the input signal is sampled. At the end of the conversion, the buffer input is connected to the AIN terminal again, and the holding capacitor tracks the input voltage. Whenever the conversion is not in progress, T/H is in tracking mode. After the start of the conversion, the hold mode starts with approximately 10ns (window delay). The typical time delay variation from one conversion to the next is 30ps (window jitter).

Circuit clock frequency

MAX121 requires a clock compatible with TTL and CMOS levels when working, and the clock frequency ranges from 0.1 to 5.5MHz. To meet the acquisition time requirement of 400ns in 2 clock cycles, the maximum clock frequency is limited to 5MHz. Due to the limitation of the internal T/H voltage drop rate, the clock frequency of all modes should not be lower than 0.1MHz.

Output data

The conversion result is output as a 16-bit serial data stream, with the first 14 bits as data bits (MSB first) and the last 2 bits as zero. The output data is in binary complement form. At the rising edge of CLKIN, the data is synchronously output at the SDATA end. The output data can be framed using FSTRT or SFRM output. Each conversion is required to be at least 18 clock cycles to obtain a valid output.

Design and Programming

MAX121 has three working modes:

1) Conversion controlled by /CONVST;

2) Conversion controlled by /CS;

3) Continuous mode.

The first of the three modes is used to connect with DSP and other microprocessors, the second is used for multiple device combination applications, and the third MAX121 works in a continuous conversion state and is used for continuous sampling of data.

In mode 1, there are two clock supply modes, one of which is provided by CLKR. The principle block diagram is shown in Figure 4.

However, this connection method can only provide a maximum clock of 3.2MHz. In addition, the clock can be provided by an external circuit, which can reach the maximum clock of the system of 5.5MHz, realizing high-speed connection. According to the design requirements, the second connection method is selected in actual use. The specific circuit design is shown in Figure 5.

CLKIN (14) is connected to an external active oscillator to provide a 5MHz clock;

MODE (16) is connected to the +5v power supply, /CS is grounded: select the working mode;

/CONVST (13) is connected to the XF pin of TMS320VC5402 , and the data conversion is controlled by the DSP through XF; SCLK (12), FSTRT (10), SDATA (11) are connected to BLCKR0, BFSR0, BDR0 of the DSP respectively to transmit clock, frame synchronization signal, and data.

CLKIN is the input clock of MAX121, while SCLK shifts data into MAX121. CLKIN is driven by an external clock oscillator (5MHz). The XF pin (general purpose I/O port) of TMS320VC5402 drives the input of MAX121 low, starting a conversion. The BCLKR0 (receive clock) terminal of TMS320VC5402 is configured as an input and driven by the SCLK output terminal of MAX121. The data of SDATA output terminal of MAX121 changes state on the rising edge of the clock, and on the falling edge of the clock, the data is latched into the DR input terminal of TMS320VC5402. This provides 1/2 clock cycle to meet the data setup and hold time required at the DR input terminal. The maximum skew between MAX121 SCLK and SDATA is 65ns at +25, so 1/2 clock cycle is enough to meet the required setup and hold time. The working timing is shown in Figure 6.