Application of CPLD in DSP Multi-resolution Image Acquisition System

The video acquisition system is the most basic means of acquiring digital images and the premise for digital image processing, multimedia and network transmission. It can provide the original digital images to be processed and the algorithm verification platform for various image processing algorithms. With the rapid development of image digital processing technology, the requirements for image acquisition are getting higher and higher, including the requirements for the speed, subjective quality, flexibility and so on of the acquired images. In response to this development trend, a multi-resolution image acquisition and processing system based on CPLD and DSP devices is designed, focusing on the flexible application of CPLD logic control in the acquisition process.

3.2 Bus Logic Switching Design

As mentioned above, the bus switching management between CPLD and DSP is a difficult point in the design. During the data acquisition process, CPLD must master the bus control, and during the data processing process, DSP must master the bus control. In order to solve this seamless switching problem, the DSP's hold request signal nHOLD and hold response signal nHOLDA are fully utilized to coordinate the bus switching [3].

By setting the XF pin of DSP to low level, the CPLD is told to start controlling SAA7111A for image acquisition. When DSP_XF is connected to CPLD at high level (DSP_XF should be initially at low level), CPLD generates DSP_HOLD bus request switching signal, which is connected to the nHOLD pin of DSP to request DSP to enter the hold state. After 3 machine cycles, DSP responds by generating nHOLDA low level signal to CPLD, and the external data bus, external address bus and control bus all become high impedance. At this time, DSP enters the hold state, and CPLD controls the operation of each bus. When a frame of image is acquired and stored, CPLD generates nINT interrupt signal to notify DSP to start processing data, and at the same time sets DSP_HOLD pin high so that nHOLD pin of DSP is also set high. By programming CPLD, each external data bus, external address bus and control bus connecting CPLD and SRAM are set to high impedance state. After nHOLD is set high for 3 machine cycles, DSP external data bus, external address bus and control bus are out of high impedance state, DSP enters normal working state, DSP sets XF pin to high level, takes back bus control right to process data.

When DSP transmits the processed frame data to the host computer, it sets the XF pin low again to tell CPLD that it can start collecting the next frame. CPLD generates DSP_HOLD to put DSP into the hold state, and the external data bus, external address bus and control bus all become high impedance again, and CPLD takes control of the bus. This reciprocating process can solve the bus conflict problem between DSP and image acquisition module, and the correct switching bus logic ensures that images can be collected and processed cyclically.

3.3 CPLD logic function simulation verification

By using CPLD to control the image acquisition process of the video A/D chip SAA7111A, and using the output status signal of SAA7111A to control CPLD to realize image data storage, timing control, address decoding and other functions. This well coordinates the timing relationship between the line and field reference and synchronization signals, pixel clock, SRAM read and write signals and DSP control signals, ensures the timing coordination of each signal during the SRAM read and write operation, and solves the line and field delay problem well, so that the image resolution transitions from 720×625 to 640×480, and correctly generates the SRAM write address, DSP interrupt signal and bus switching signal.

Due to limited space, the specific VHDL code is not listed. Only the simulation results are given. The simulation results are as follows:

Figure 4: Cyclic acquisition and processing simulation diagram

The above cyclic acquisition processing simulation diagram is the timing logic relationship of each signal in the acquisition module when the actual system is working. From the simulation diagram, it can be seen that the multi-point line and field delay and odd and even field separation storage are realized through the programming of CPLD, so as to obtain multi-resolution image data, and the DSP interrupt generation, logic bus switching signal, start trigger signal of the next frame, odd and even field alignment signal, etc. can meet the system timing requirements. It takes about 22.75ms to acquire a frame of 640×480 image, which can meet the real-time requirements.

4 Conclusion

This paper designs a multi-resolution image acquisition system based on CPLD. The author's innovation is to propose a method to obtain image data of different resolutions by controlling the delay of line and field signals of the image by CPLD, and storing the odd and even data separately, so as to realize the real-time acquisition of multi-resolution images without occupying DSP resources. After a lot of simulation and circuit board debugging, it is proved that this scheme is flexible and effective, and can be widely used in the fields of real-time image acquisition such as industrial monitoring and medical diagnosis.

2 System Design

According to the system requirements, an independent acquisition method is adopted, and a dedicated image acquisition chip is used to automatically complete the image acquisition. In addition to setting the acquisition mode, the processor does not participate in the acquisition process. The characteristics of this method are that it does not take up CPU time, has good real-time performance, and is suitable for the acquisition of active images. The system design process is as follows: DSP sends a start acquisition instruction, A./D starts acquisition, and the control and status signals output by A/D are connected to CPLD. The CPLD controls the storage of the converted digital signal in the high-speed and large-capacity SRAM (ODD and EVEN) until a frame of image data is stored. During this period, CPLD generates SRAM address, SRAM read and write signal, interrupt signal, bus switching signal, etc.; CPLD hands over the bus control, and DSP occupies the bus to read the image data from SRAM for processing. Due to space limitations, this article focuses on the flexible design of CPLD in data acquisition. The system structure is shown in the figure below:

Figure 1: System structure diagram

3 System Hardware Design

The DSP of this system is TMS320VC5416 in the 54x series produced by TI , and the CPLD is EPM7128A in the MAX7000 series of ALTERA. The A/D chip is SAA7111A video A/D conversion chip produced by Philips. Here, the DSP multi-channel buffered serial port McBSP is used to simulate the I2C bus timing to initialize SAA7111 A.

3.1 Logical function design of data acquisition

This design scheme uses CPLD to control the video acquisition chip SAA7111A to achieve line and field data delay [2], and separates the odd and even field data for storage. The DSP selects to read the acquired odd and even field data and processes them together or separately, thereby obtaining multi-resolution image data. The control signal and status signal generated by SAA7111A are connected to the CPLD, that is, the vertical synchronization signal VREF, the horizontal synchronization signal HREF, the odd and even field flag signal RTS0, the chip select signal CE, the field synchronization signal VS, the pixel synchronization signal LLC2, etc. are connected to the CPLD. The CPLD performs operations such as decoding and generating storage addresses through these control and status signals. The time between the two positive pulses of the vertical synchronization signal VREF is the timing for scanning a frame (frame scanning mode) or a field (field scanning mode), that is, a complete frame or field image is scanned between the two positive pulses. The horizontal synchronization signal HREF is the timing for scanning each row of pixels in the frame or field image, that is, when it is high, it is the effective time for scanning a row of pixels. If the current image window size is 640×480, there are 480 HREF positive pulses between the two VREF positive pulses, that is, 480 lines; during each HREF positive pulse, there are 640 LLC2 positive pulses, that is, 640 pixels per line, that is, the relationship between the three synchronization signals VREF, HREF, and LLC2.

In order to reflect the multi-resolution characteristics of this system, it is necessary to change the default sampling resolution of SAA7111A, and multi-resolution image data can be obtained through the logic control of CPLD. This article chooses to collect from the default resolution 720×625 to the set resolution 640×480, so it is necessary to perform field delay and discard some pixels. By writing the I2C register line synchronization start register (subaddress 06) and line synchronization end register (subaddress 07) in SAA7111A, the effective time of line synchronization can be directly controlled, so the line delay circuit design can be omitted, and the field delay is implemented in CPLD.

The logic function design is roughly divided into the following parts: bus switching logic between DSP and CPLD; field delay part (counter design for the falling edge of HREF); SRAM address generation part controlled by LLC2; SRAM chip select signal, write signal and synchronous clock selection timing control part. Among them, the bus management between CPLD and DSP is the difficulty in the design. The image acquisition timing is shown in the figure below.

Figure 2: Image acquisition timing diagram

The specific description is as follows: Setting the XF pin of the DSP low generates the START acquisition start signal, which sends an image acquisition command to the CPLD. When the VS rising edge comes, if RTS0 is low, it indicates that the odd field is coming, and the ODD high-level signal is generated. The ODD is inverted and then used as the chip select signal CS_ODD of the SRAM (ODD) after being phase-ORed with the nPS output by the DSP. At the rising edge of VREF, the field delay counter is started. The field delay is implemented in the CPLD. From 625 lines per frame to 480 lines, 145 lines need to be discarded (240 lines are collected for odd and even fields respectively). The line synchronization reference signal HREF is used in the CPLD to design the counter (HREF<240). At the end of the field delay, the HREF145 signal is set high, and valid image data acquisition begins to be accepted. When VREF has a falling edge, the HREF145 signal is set low, and the odd field image acquisition is completed. If RTS0 is high, it indicates that the even field is about to come, and a high-level EVEN signal is generated. EVEN is inverted and then phase-ORed with the nPS output by the DSP and used as the chip select signal CS_EVEN of the SRAM (EVEN). The field delay is still implemented by using the horizontal synchronization reference signal HREF for counter design (HREF<240). At the end of the field delay, the HREF145 signal is set high, and valid image data acquisition begins to be accepted. When VREF has a falling edge, the HREF145 signal is set low, and the even field image acquisition is completed. In addition, the GCSWITCH signal is used as the control signal for the CPLD to select the internal clock. When GCSWITCH is at a high level, it means that the CPLD obtains the bus right, the system is in the image acquisition stage, and the CPLD internal clock is LLC2; when GCSWITCH is at a low level, it means that the DSP takes back the bus right, and the system is in the image processing stage. At this time, the clock signal inside the CPLD is the DSP output clock signal CLOCKOUT. The odd and even field image memory uses ISSI's 10ns-level 256K×16 high-speed SRAM, and the LLC2 clock is 13.5MHz, that is, each pixel clock is about 74.1ns. Each LLC2 pulse generates an SRAM address, which can fully meet the requirements relative to the 10ns-level read and write cycle of the SRAM. The write logic timing control design using the LLC2 (about 13.5MHz) clock is shown in the figure below:

Figure 3: RAM (ODD, EVEN) write signal timing diagram

At the same time, please note that if the image data has entered the even field or odd field when the next frame is collected after processing one frame of image, if the image collection is enabled at this time, the collected image will be incomplete because it does not start from the image header, so it is necessary to determine the benchmark for the start of image collection. Here, the design detects whether the image collection start signal is generated only at the rising edge of RTS0, so that each frame of image is collected only at the rising edge of RTS0, that is, it starts from the even field each time, thus avoiding the confusion of image data and ensuring the starting benchmark of the image. In addition, since the SRAM (odd and even field SRAM) address storing image data is generated by CPLD control, if the VPO[15:0] converted and output by SAA7111A is directly stored in SRAM, it will inevitably affect the synchronization of data and address, resulting in different data being written to the same address, and the same data being written to different addresses, thus causing read and write errors. Therefore, consider using the VPO[15:0] output by SAA7111A as the input signal of CPLD, and then connect it to the data line of SRAM after synchronization processing through delay in CPLD, so that the timing requirements can be met and the data can be written to the correct address.