Data communication between CY7C68013 and FPGA in Ports mode

introduction

Universal Serial Bus (USB) has the advantages of fast, bidirectional, high-volume transmission, cheapness, and hot-swappability. CY7C68013, one of Cypress's FX2 series chips, is the earliest microcontroller that complies with the USB2.0 standard and integrates The USB2.0 transceiver, serial interface engine (SIE), enhanced 8051 core and programmable peripheral interface realize interface data communication based on USB2.0. CY7C68013 can be configured into 3 different interface modes; Ports mode), GPIF Master (programmable interface mode) and Slave FIFO (master-slave mode). Among them, the latter two modes use their internally integrated hardware (USB core) that can automatically handle USB transactions independently of the microprocessor. Data The transmission is completed by executing the USB protocol itself, and the microprocessor does not need to participate in the data transmission, thereby greatly increasing the data transmission rate and simplifying the writing of firmware code. Since the latter two methods overcome the bandwidth "bottleneck" of the microprocessor, they are widely used in large-scale data transmission, such as the collection of images, videos and other signals.

The former Ports (port mode) is rarely introduced in the literature. As the most basic data transmission method, its data transmission is mainly completed by the firmware program and requires the participation of the CPU. Therefore, the data transmission rate is relatively low and is suitable for In situations where the transmission rate is not high, and because FX2 integrates an 8051 core, it is an effective data transmission method for an engineer who has just transitioned from microcontroller development to USB development. Now, a project The developed example will explain in detail how to realize two-way transmission of data in Ports mode.

1 Design requirements

The host sends data sequences to the two channels through the USB interface at a rate of 4KB/s, and the peripheral D/A converter completes the data conversion. At the same time, the two external A/D converters transmit data at a rate of 400KB/s. The sampling rate completes the data collection, and the collected digital signals are also transmitted to the host storage through the USB interface. Among them, the USB interface chip uses Cypress's CY7C68013, and the FPGA uses Altera's EP1C6Q240C8. Figure 1 is its data multiplex transmission system. block diagram.

2 USB data multiplexing hardware

2.1 EZ-USB FX2 CY7C68013

EZ-USB FX2 CY7C68013 supports USB2.0 data transmission. Its internal structure and functions have been introduced in detail in other documents. Here is a brief description of the role of this chip in this circuit. The Ports interface mode of CY7C68013 is mainly used in the design. To complete the transmission of multi-channel data, the transmission of data and status between USB and FPGA is completed by the IOA interface of CY7C68013. The IOB0-IOB2 port line in the IOB interface serves as the control line between USB and FPGA. The EP2 port inside CY7C68013 is set to 512-byte double buffering, OUT, and block transmission, and is used as a buffer for the host to send data to peripherals; the EP6 port is set to 512-byte double buffering, IN, and block transmission, and is used to transmit data to peripherals. Data buffer.

2.2 FPGA chip EP1C6Q240C8

The FPGA uses Altera's Cyclone chip EP1C6Q240C8. The FPGA has three functions here: First, allocate two 128×8-bit RAM areas to each of the two D/A conversion channels as a buffer for sending data from the host to the peripheral. Second, allocate two 512×8-bit RAM areas to each of the two A/D conversion channels as a cache for transmitting data from the peripheral to the host. Since the transmission and acquisition of the two-channel data share an 8-bit data bus, so , the data bus needs to switch back and forth for different reception and transmission, so each channel uses two RAM blocks respectively to act as a double buffer to prevent data "overflow" during transmission. Third, since the data bus needs to switch back and forth for different channels, the process of controlling the switching is completed by the status register. Therefore, a status register must be set inside the FPGA. The set status register only contains two bits to identify the two channels respectively. The "full" or "empty" status of the data RAM to determine which channel should currently send or receive data.

3. Formulation of communication protocol

The Ports mode of CY7C68013 is used to implement data communication. Different from the FIFO and GPIF modes, the latter two modes are mainly completed by the USB core in terms of data transmission, and the required control signals are provided by CY7C68013 itself. For Ports mode, the control signal does not have a dedicated port line, so it must be completed with other general-purpose I/O interfaces. Here, IOB0-IOB2 is used as the control line between USB and FPGA. Due to the three customized The lines are general port lines and have no practical significance. Therefore, the communication protocol between USB and FPGA must first be formulated, that is, to give actual functions to these three port lines.

ALE (IOB0): For example, the rising edge of ALE transmits control instructions to the FPGA through the IOA port. For example, when IOA=01H, it means that the system starts to work and the A/D and D/A converters start. When IOA=88H, it means that the conversion is over, and the FPGA will no longer receive or send data. When IOA=02H, it means that CY7C68013 will read the contents of the status register in the FPGA, by reading 0 or 1 of the two status flag bits. Determine the "full" or "empty" status of the four data buffers in the two channels. If any data buffer of the D/A channel is "empty", the FPGA will set the first status flag of the status register to Fill in 1; otherwise fill in 0; similarly, if any data buffer of the A/D channel is "full", the FPGA will fill in 1 in the second status flag bit of the status register; otherwise fill in 0; when IOA =03H, it means that the host will send conversion data to the D/A channel through USB, sending 256 bytes each time. The first 128 bytes are channel 1 of D/A conversion, and the last 128 bytes are channel 2. When IOA= When 04H, it means that the host will receive the data transmitted by the A/D channel.

RD (IOB1): Use the rising edge of RD to read the data converted by the D/A converter through the IOA port.

WR (IOB2): Use the rising edge of WR to send the data transmitted by the host to the A/D converter through the IOA port.

4 Software implementation

The data transmission between USB and FPGA in Ports mode is implemented by the CPU core inside CY7C68013. Therefore, the writing of firmware programs is more important. In general, there are two ways to write firmware programs: one. Since CY7C68013 integrates an enhanced 8051 core, users who are familiar with 8051 assembly language can directly use assembly language to write efficient firmware code; secondly, Cypress's EZ-USB FX2 series is equipped with ready-made firmware program framework functions , when users need it, they only need to add the corresponding user program. Of course, the implementation of data communication in the user program is also the process of how to complete the communication protocol.

Here, the latter is used to complete the data communication between CY7C68013 and FPGA. Some of the software codes to implement the data communication function are as follows (the following codes can be written in the framework function void TD_Poll (void)):

5 Summary

In the data communication between CY7C68013 and FPGA, the basic Ports interface mode is used, the automatic pointer method is used, and through observation with a digital oscilloscope, it takes about 750μs to complete the transmission of 1KB. Compared with the other two modes, although the data transmission speed is lower, as a data transmission mode, it is also an effective development method, especially for engineers who have just transitioned from microcontroller development to USB development.