Hardware Design of Data Recorder and Analyzer Based on Embedded System

Abstract: In order to centrally monitor a large number of automated instruments in industrial sites and improve the level of automation in industrial production, a data recorder and analyzer for power equipment is designed with S3C2410A as the main control chip, LCD screen as the display device, touch screen as the input device, and SD card as the storage device. The recorder supports CAN communication and 485 communication to collect data from the sampling module. It has a large-screen display output, simple and easy touch screen input, Ethernet to upload data, large-capacity storage space, complete functions, and a wide range of uses.

The system designed in this paper is to meet the needs of real-time recording and timely analysis of relevant data of each device . This system is based on S3C2410, adopts Linux real-time operating system, combines the advantages of embedded devices and network technology, has the advantages of large number of connected devices, fast speed, multiple functions and strong scalability, etc., can complete the centralized monitoring of a large number of power equipment, significantly improve the reliability of user automation system, and save a lot of manpower and material resources.

The electric power equipment recorder based on S3C2410 uses the powerful ARM920T core chip as the CPU, supports 485, CAN, Ethernet three communication methods, uses LCD display and touch screen, and large-capacity SD card storage unit.

1 Overall structural design of the system

The components and main functions of the system are as follows:

1) The host computer part is mainly responsible for remote information configuration and data collection, recording, and processing.

2) Data recording and analysis part: mainly responsible for on-site information configuration and data recording and processing.

3) Single chip microcomputer system: mainly responsible for the collection, monitoring and processing of environmental information.

2 System Hardware Design

The hardware system of the recorder consists of two parts: the core board and the main board. The core board is mainly responsible for the construction of the CPU, RAM memory, Flash memory, etc.

The mainboard includes the power supply part of the whole system, Ethernet communication part, CAN communication part, 485 communication part, serial communication part, display part, data storage part, CPLD part, etc. The core board is connected to the mainboard through a double-row pin structure.

The block diagram of the hardware design is shown in Figure 1.

Figure 1 Recorder structure diagram

2.1 Design of the core board

The core board is mainly composed of CPU S3C2410, memory SDRAM, flash memory NANDFlash, crystal oscillator circuit, startup configuration circuit and other parts.

The CPU S3C2410A only integrates 4k SRAM inside, which is used as the boot program space of the system program, so it is necessary to expand a certain capacity of RAM to be used as the running space, data and stack area of ​​the main program. When the system starts, the CPU first reads the startup code from the reset address 0x0. After the system initialization is completed, the program code is generally transferred to the SDRAM to run in order to improve the running speed of the system. At the same time, the system and user stacks and running data are also placed in the SDRAM. After the boot program in the SRAM is completed, the operating system image will be loaded into the SDRAM. The SDRAM of this system is constructed by two HY57V561620T chips into a 32-bit SDRAM storage structure.

HY57V561620T is a 268 435 456-bit CMOS SDRAM chip that can well meet the storage needs of large capacity and high width.

The Flash used in this system is Samsung's K9F1208. It has a capacity of 64 MB and adopts block-page storage management. Its 8 I/O pins serve as multiplexed ports for data, address, and command.

2.2 Motherboard Design

As mentioned above, the mainboard is responsible for the power supply part, Ethernet communication part, CAN communication part, 485 communication part, serial communication part, display part, data storage part, CPLD part, etc. of the entire system.

2.2.1 Design of power module

Each module of the CPUS3C2410A chip adopts independent power supply. Among them, when the core works at 200 MHz, the working voltage is 1.8 V, when it works at 266 MHz, the working voltage is 2 V, and the working voltage of the memory and I/O is 3.3 V. Therefore, this system uses a +5 V switching power supply module, and then processes the +5 V voltage into 3.3 V and 1.8 V voltage respectively. Among them, the 3.3 V voltage is obtained by adjusting +5 V with a low voltage difference linear voltage source. The DC 5 V voltage is connected externally, filtered by the power supply, and outputs a stable, usable 5 V voltage. Through the adjustment of LM1117T, a usable 3.3 V voltage can be obtained. Finally, a 100 μF tantalum capacitor is connected to the output end to improve its transient response and stability.

The schematic diagram is shown in Figure 2.

Figure 2 3.3 V voltage implementation

The 1.8 V in the system is converted from 3.3 V by the linear voltage regulator MIC5207, and its schematic diagram is shown in Figure 3. The output voltage is used to power the CPU core. In the figure above, the 3rd pin of MIC5207 is connected to the PWREN pin of the CPU. By giving the MIC5207 a level through PWREN, the switch of MIC5207 can be controlled, so that the power supply of the CPU core can be turned off and put into the power-off state. The 4th pin of MIC5207 is connected to a 470 pF bypass capacitor, which is used to further reduce noise. Its output is connected to a 470 pF filter capacitor to further make the output more stable.

Figure 3 1.8 V voltage implementation

2.2.2 Design of communication module

As a multifunctional data recording and display instrument, this system provides 485 communication and CAN communication to connect with the lower computer sampling module. 485 communication and CAN communication are two commonly used modules in industrial sites. In addition, the system is also equipped with an Ethernet communication module to facilitate data transmission to the upper computer for centralized monitoring and management. Below, we will briefly explain them respectively.

1) Design of 485 communication module

The schematic diagram of the 485 communication module is shown in Figure 4.

Figure 4 Schematic diagram of 485 communication module

Conventional 485 communication modules are composed of power isolation, optocoupler electrical isolation, RS-485 bus transceiver and protector. Due to the existence of the ground loop, there is a potential difference between the communication loop and the ground, which is particularly prominent in harsh environments. The potential difference will form a common-mode voltage between the communication lines. Due to the unbalanced impedance between the communication lines to the ground, the common-mode voltage will generate interference voltage between the communication lines, reducing the reliability of communication, and in severe cases, it will also destroy the communication node. The role of power isolation and optocoupler isolation is to prevent this from happening, but adding too many isolation modules will complicate the circuit. In this system, an integrated isolated 485 transceiver module RSM485CHT is used, which integrates power isolation, optocoupler electrical isolation, bus transceiver and bus protector. This reduces the complexity of the system and effectively improves the anti-interference ability, transmission speed and reliability of the circuit. It also effectively reduces the area of ​​the PCB board and the complexity of the wiring.

Since the interface matching level of TXD, RXD, CON of RSM485CHT chip is +5 V level, and the pin level of CPU is 3.3 V, it is necessary to connect a bus level converter 74LV4245A to provide interface for 3 V devices and 5 V devices. You can also choose the isolation module RSM3485CHT that matches 3.3 V level.

2) Design of CAN communication module

CAN bus was developed by BOSCH and was first used in the automotive industry to solve the communication between the huge electronic control devices in modern cars and reduce the increasing signal lines. It is a multi-master serial communication bus with high bit rate, high anti-electromagnetic interference, low cost, high transmission efficiency, long transmission distance, and reliable error handling and error detection mechanism. Because CAN bus has good real-time performance, it has been widely used in the automotive industry, aviation industry, industrial control, and safety protection fields.

Since the invention of CAN bus, many CAN control chips have appeared, each with its own advantages. The control chip used in this article is SJA1000T from PHILIPS. SJA1000 is an independent controller that adds a new mode to support CAN2.0B protocol. It is a substitute for 82C200. Compared with the latter, its performance in all aspects has been greatly improved. The identifier has been expanded from 11 bits to 29 bits, and the filtering mode has been changed from the original single mode to single filtering and dual filtering. In addition, there have been great improvements in error handling, overload capacity, and acceptance filtering.

Similar to the 485 communication module, the design of the CAN communication module still uses the isolation module CTM1050. CTM1050 is used as the interface between the physical bus and the CAN controller to improve the differential transmission capability of the bus and the differential reception capability of the CAN bus. CTM1050 uses a full potting process, and integrates all the transceiver circuits required for the CAN bus, completely electrically isolates the circuit, and isolates the voltage. It well implements the modular design of the system and simplifies the connection and maintenance of the circuit. The schematic diagram of the CAN bus module is shown in Figure 5.

Figure 5 CAN communication module schematic diagram

As shown in the figure above, the CAN bus communication module consists of the CAN controller SJA1000T and the integrated transceiver controller CTM1050. The CAN transceiver is connected to the CAN bus and is responsible for controlling the logic level signal from the CAN controller to the bus physical layer or vice versa. The upper layer of the CAN transceiver is the CAN controller, which is responsible for executing the complete protocol in the CAN specification and is usually used for message buffering and acceptance filtering. The upper layer of the CAN controller is the CPU.

SJA1000 supports two CPU types: 80C51 and 68**. This function is achieved by configuring the MODE pin. In this system, the INTEL mode of 80C51 is used. In addition, an independent external crystal oscillator is used to improve the EMC performance of the CAN node.

3) Design of Ethernet communication module

The Ethernet interface in the monitor is designed to communicate with the host computer through the configuration software, thereby improving the automation level of the entire system and increasing operability.

The Ethernet interface controller mainly consists of two parts: MAC and PHY. The MAC layer control is easier to carry inside the processor as a logical control. For embedded processors without integrated MAC controllers, a more common method is to use an Ethernet controller that integrates MAC controller and PHY. This system adopts this method. There are many controllers with Host Bus interface. This system uses CS8900 from Cirrus Logic[5].

CS8900A is a true single-chip, full-duplex Ethernet controller that integrates all required analog and digital circuits into a complete Ethernet circuit. It consists of the following modules: direct ISA-bus interface, interface buffer memory, serial EEPROM interface, complete analog filter with 10ASE-T port and AUI port.

CS8900 can be set to test mode and sleep mode, low level is effective, and nTEXT and nSLEEP are set to high in normal mode. CS8900A-CQ3 is a 3.3 V chip. It can be directly connected to S3C2410. In this system, a tri-state gate is connected between the address bus and the CPU and between the data bus and the CPU, so that the bus can be effectively controlled. In addition, the CPLD module replaces the commonly used NAND gate circuit, saving the CPU pins and reducing the size of the circuit board. The circuit schematic is shown in Figure 6.

Figure 6 Ethernet module schematic

The display module of the system uses an 800×600 LCD screen and a resistive touch screen with a relatively simple structure. Due to space limitations, it will not be described here.

3 Conclusion

This design can centralize the equipment data scattered in various work sites, and can complete the centralized display and analysis of data, and the operation and control of each unit equipment. It can also serve as an intermediate station for data transmission, and transmit data to the host computer for centralized detection and control. In the network of industrial sites, it can play a very critical role. In addition, the system is highly versatile and can be applied to many occasions with different software definitions.