PLDs manage image data in automotive infotainment applications

Infotainment systems help drivers get to their destination safely while entertaining passengers, and they are no longer exclusive to premium vehicles: now emerging driver-assistance systems are entering the mainstream. The front LCD needs to dynamically switch from a GPS display to one of many cameras, or even a combination of images captured by several cameras around the vehicle. Images from the rear cameras assist with parallel parking, ensuring that parking spaces are left and lanes are safely navigated, and avoiding collisions with oncoming vehicles. To expand the driver's field of view at busy intersections, images can be displayed from the front cameras (two cameras mounted on the body above the two front wheels). Some vehicles are able to provide a "look around image," which is basically a virtual 360-degree view around the vehicle body, with images from cameras in the front (the tip of the hood), rear, and sides (side mirrors). For different sized LCD screens, these images may need to be scaled (sized), adjusted, and enhanced to improve image quality.

Managing image data requires new ICs. ASICs are expensive and risky, while ASSPs are inflexible. Programmable logic devices (PLDs) overcome these drawbacks, but they face interface challenges for image data, which often require high performance, and are expensive to use. However, this situation is changing. A new generation of low-cost PLDs with high-performance IO buffers is now available. These low-cost PLDs provide efficient transmission, processing, manipulation, and display of digital data while enabling product differentiation and helping achieve time-to-market and cost-effectiveness goals.

Transmitting image data

Various methods are used to transmit image data in vehicles. One common method is to use LVDS to establish a source synchronous interface.

A popular technology for video applications is to use a 7:1 LVDS (Low Voltage Differential Signaling) interface. ChannelLink, CameraLink, Flat Panel DisplayLink, and FlatLink are variations of this approach. LVDS is a high-speed, low-power, universal interface standard. It uses a pair of differential signals that produce equal and opposite currents, which also helps reduce overall radiated emissions. In addition, LVDS uses current-mode drive, which limits power consumption. National Semiconductor developed LVDS-based ChannelLink and FPDLink (Flat Panel DisplayLink) technologies as a solution for flat panel displays, supporting data transfer from the graphics controller to the LCD panel. The technology was later expanded to a universal data transfer method. CameraLink is a 7:1 LVDS-based standard that uses up to 28 bits of data and can reach clock rates of 85Gpbs for a total throughput of 2.38 MHz. Texas Instruments’ FlatLink is available in 21:3 or 28:4 configurations and supports 4-bit, 6-bit, or 8-bit RGB.

Challenge of implementing LVDS7:1 with low-cost programmable logic devices

7:1 LVDS interfaces typically use three to five LVDS data channels and one LVDS clock channel. Higher resolution displays may use four or five LVDS data channels. In one clock cycle or period, there are seven serial bits in each data channel, as shown in Figure 1.

Figure 1 7:1 LVDS interface timing

The challenges of implementing a 7:1 LVDS interface with low-cost programmable logic devices include high-speed LVDS buffers and PLLs for generating the deserialization clock, being able to capture the incoming data with high efficiency, and accurate matching and data formatting.

High-speed LVDS buffers: Must be able to receive or send data and clocks to or from the programmable logic device at relatively high speeds. The exact speed depends on the resolution, frame rate, and color depth used by the display. For example, 800×600 to 1024×768 displays require LVDS data transmission frequencies from 40 MHz to 78.5 MHz for refresh rates of 60 Hz to 75 Hz. This translates to LVDS data rates of 280Mbps to 549Mbps. Higher resolution displays, such as 1280×1024, 60 Hz, require that the data must be transmitted with a 108MHz clock. For these systems, data is transmitted at 756 Mbps.

Clock Generator: The usual approach is to take the incoming clock and use a phase-locked loop to multiply the clock frequency by 7 for each data bit. In practice, this is quite difficult because the clock runs extremely fast. Since typical display interface clock rates are 60MHz to 100MHz or higher, multiplying by 7 produces frequencies of 420MHz to 700MHz. Operating at these clock rates, any image control and processing is impossible to implement with a low-cost PLD.

Data Capture, Matching, and Formatting: The registers immediately following the LVDS input buffers must accurately capture the data. Tight control of the clock and data relationship is important to capture the incoming high-speed data stream. It is also necessary to match (reduce) the data speed that is passed to the PLD earlier. If the input capture circuit runs on only one clock edge, seven phase shifts of lower speed clocks should be generated to capture the input data with seven different registers. The challenges of clock generation and distribution hinder implementation with PLDs. The clock must have relatively low jitter because its jitter must be calculated in the overall timing budget. Also, the skew of the clock distribution network used to provide the clock input or output register must be considered in any timing analysis.

Example of implementing 7:1 LVDS in MachXO2 devices

The programmable logic device MachXO2 has a function-specific architecture that supports 7:1 LVDS interfaces. These features include high-performance LVDS I/O buffers, double data rate (DDR) I/O registers, matching logic, and a high-precision phase-locked loop with a dedicated 3.5 clock divider. These features and functions provide a complete solution. MachXO2 devices provide up to 21 data channels. Figure 2 shows the four data channels of the receiver and transmitter.

Figure 2 Receiver and transmitter in MachXO2

In this figure, the receive module of the MachXO2 device receives four channels of data and the clock through LVDS I/O buffers. These buffers can run up to 303 MHz (606 Mbps), supporting high resolution, display refresh rates up to 85 MHz pixel rate (SXGA). The PLL multiplies the clock by 3.5. The faster phase-shifted clock (ECLK) is then distributed through a low skew edge clock net to the DDR capture registers. The LVDS data is fed into the DDR registers with 7:1 matching. This matching allows the I/O data to be demultiplexed from the high speed EDGE clock (ECLK) and then to the slower FPGA clock frequency (SCLK).

This 7:1 LVDS solution includes automatic alignment of the PLL output clock to the optimal position for sampling the input LVDS data stream, and adding logic to automatically align the PLD clock to the input data word. These "soft" logics work in conjunction with the "hard" resources to provide a complete display interface solution.

The MachXO2 PLD's transmitter module receives 28-bit parallel data and a fast DDR clock (ECLK). The parallel data is fed into the display I/O logic unit with a 7:1 matching function. The matching function allows the input data with a low-speed system clock (SCLK) to be multiplexed to the higher speed DDR output edge clock rate (ECLK).

Summarize

The addition of digital content, rear seat displays and navigation systems with many image sources (several cameras) are entering the mainstream market.

In graphics applications, the 7:1 LVS interface is expected to remain popular due to its cost and power consumption advantages, such as in-vehicle infotainment systems.

MachXO2 devices can be deployed in automotive driver assistance systems to manage the display and manipulation (zoom, rotate, etc.) of images from cameras. MachXO2 devices can dynamically switch between displaying images from one camera to another, or a combination of the two.