Principle Analysis and Design of Machine Vision System Module

1. Overview

Vision technology is an emerging technology developed in recent decades. Machine vision can replace human vision to carry out inspection, target tracking, robot guidance and other tasks, especially in those occasions where accurate information needs to be obtained from images repeatedly and quickly. Although under the current hardware and software technical conditions, the function of machine vision is still at a primary level, its potential application value has attracted great attention from countries around the world. Developed countries such as the United States, Japan, Germany, France, etc. have invested a lot of manpower and material resources in research. In recent years, breakthrough progress has been made in certain aspects of machine vision. Machine vision is also increasingly showing its important value in applications such as vehicle safety technology and automation technology. This paper designs a universal visual system module based on the latest CMOS image acquisition chip. After compiling different image processing and pattern recognition algorithm programs, this module can be applied to various occasions such as football robots and unmanned vehicles.

2. Design Principle

The system principle block diagram is shown in Figure 1.

The system consists of five main chips: image acquisition chip OV7620, high-speed microprocessor SH4, large-scale programmable array FPGA, and serial communication control chip MAX232. Two dual-port RAMs are programmed inside the FPGA to generate the dot frequency, line field synchronization and other signals required by the image sensor, as well as control the storage timing of the dual-port RAM. SH4 is responsible for configuring OV7620 through I2C, reading the image data from the dual-port RAM, processing it, and uploading image data or controlling other devices such as stepper motors through the serial port.

3. Image Acquisition Module

The system module is based on the CMOS image sensor OV7620, and also includes a focusing lens and some other auxiliary components such as a 27MHZ crystal oscillator, resistors and capacitors.

COMS image sensor is a new type of image sensor that has developed rapidly in recent years. Due to the use of the same COMS technology, the pixel array and peripheral support circuits can be integrated on the same chip, which is a complete image system (Camera on Chip). This system uses a CMOS color image sensor OV7620 launched by Ommnvision with a resolution of 640x480. It can work in progressive scanning mode or interlaced scanning mode. It can not only output color images, but also be used as a black and white image sensor. This chip supports many image output formats: 1) YCrCb4:2:2 16 bit/8 bit format; 2) ZV port output format; 3) RGB raw data 16 bit/8 bit; 4) CCIR601/CCIR656 format. Its functions include contrast, brightness, saturation, white balance and automatic exposure, synchronization signal position and polarity output, frame rate and output format, etc. can be programmed and configured through the I2C bus. The on-chip register control.

The focusing lens is the DSL103 lens produced by Sunrise. This lens is small in size and suitable for the application of embedded vision sensors.

FPGA Interface Module

The FPGA uses Xilinx's XC2S100, which integrates 10,000 logic gates. The interface program is written in VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language). In order to increase the data transmission rate, two dual-port RAM buffers are allocated inside the XC2S100, with a size of 127KB. Each dual-port RAM stores one line of image data. The two groups of dual-port RAMs switch the odd and even row counters. When a row is stored, an interrupt request signal for reading the row data is immediately transmitted to SH4. The internal structure of the FPGA is shown in Figure 2.

The main problem here is that the dual-port RAM read and write operations inside the FPGA share the same data bus and address bus. When the read and write operations are performed at the same time, timing problems will occur, resulting in data errors in writing or reading. In order to prevent conflicts between the data and address buses in these two processes, a central bus arbitrator is designed inside the FPGA. According to the order of public data transmission, the central arbitrator first accepts the bus request of the image sensor. When the image is stored in the RAM, the central arbitrator responds to the read signal request of the microcontroller system.

Here are the structure and read-write control procedures of the dual-port RAM:

The waveform simulation diagram in MAX Plux II is shown in Figure 3:

5. MCU Module

This system uses SH4 chip as processor: SH4 microcontroller is a low-power, high-performance, RISC (Reduced Instruction Set Computer) structure full 32-bit microcontroller launched by Hitachi. Its processing speed can reach 60MIPS-100MIPS, can work at 2.25v voltage, and consumes only 400MW. It integrates 32-bit multiplier, 4-way 5KB CACHE, memory management unit MMU and other general interfaces and clock circuits. Hitachi provides C and C++ language integrated compilation tool HIM (Hitachi Integration Manager) for SH4 series microcontrollers. It can be used to compile and link Hitachi C and C++ format source programs into assembly programs or target machine codes.

The image sensor chip OV7620 has flexible programmable functions, and can be programmed through the I2C bus to set various function registers. Since the microcontroller does not have an internal hardware I2C bus interface, the I2C bus interface function can only be implemented by software simulation. The two I/O pins of SH4 are used as the SCL and SDA bus device interfaces of the I2C bus. The sample program is as follows:

This module uses the ASCII serial communication protocol that can be recognized by humans, so it can easily communicate with people through the host computer. When connected to a computer, this module can upload the entire original image data through the serial port for system debugging or more advanced image processing.

VI. Conclusion

This paper uses large-scale integrated circuit chips to form a simple and low-cost image acquisition and processing system. This system can be applied to different occasions such as football robots and agricultural product inspection robots after compiling different image processing algorithm programs. However, it also has some shortcomings, such as the SH4 processor, which has a slow computing speed and can only run some relatively simple algorithms, and does not support Ethernet interfaces. The next step is to use a dual CPU structure, in which DSP is dedicated to processing image data, and ARM is responsible for network communication and control of robot behavior. In this way, the robot's "eyes" can be connected through Ethernet into a complex collaborative processing visual system to meet the needs of more complex scenarios.