Design and implementation of a high-order audio equalization filter

As an indispensable key auxiliary adjustment device for high-quality audio, the audio equalizer plays a vital role in adjusting and modifying sound effects. Generally, there are two implementation methods for audio equalizers: digital and analog. The analog method uses active and passive filter groups. Affected by characteristics such as device temperature, it is difficult to achieve high reliability and consistency, and the cost is high. The digital implementation method uses digital filters, which have high flexibility and reliability. There are two commonly used digital filters: IIR and FIR. The IIR filter has a simple structure and requires a small storage space, but its phase is nonlinear; the FIR filter is a linear phase filter, which is necessary for high-quality sound processing. This paper designs a 1 024-order FIR filter in FPGA to implement digital equalization filtering, and realizes the equalization characteristics of multiple frequency responses by overloading the coefficients.

1. General Overview

The FIR audio equalization filter designed in this paper adopts a polyphase filtering structure, which uses time to exchange space and saves FPGA internal resources to achieve the maximum order under fixed resources. The implementation structure block diagram is shown in Figure 1.

Figure 1 Digital filter implementation structure diagram

The input sequence and filter coefficients are stored in the cache array respectively. Under clock synchronization, the control module generates the corresponding read and write addresses and enable signals to output them to the multiplication and accumulation module in a certain order for calculation and output the final result. The coefficients can be overloaded through external input to achieve different equalization characteristics. The EP1C3 series FPGA has a total of 13 M4K blocks, each of which is 256 × 18 bits, and the bit width of data and coefficients is 16 bits. In order to make full use of limited resources and consider the processing speed and audio signal rate requirements, the storage depth of each cache submodule is 256, that is, the multiplication and accumulation module is reused 256 times, and one sampling point data is calculated every 256 system clock cycles to output a filtering result. Each cache submodule occupies one M4K block. If four consecutive submodules are connected in series, the requirement of 256 x4=1 024 orders can be achieved. Considering the space occupied by the coefficients, a total of 8 M4K blocks are consumed. This is also the highest order that can be achieved under limited resources.

2 Module Implementation

2.1 Input sequence cache module

The input sequence buffer module is implemented using a dual-port RAM module, and four of them are cascaded, as shown in Figure 2. The four sub-blocks use the same read and write address and enable signal. The sampled data is input from the first sub-block, and the data output of the first sub-block is directly connected to the input of the next sub-block, and so on. The data y1~y4 of each cache sub-block is output to the multiplication and accumulation module for calculation.

Figure 2 Input sequence buffer module implementation block diagram

The key to this module is the control of the read and write addresses. The write address waddr must lag behind the read address raddr by one clock cycle, so that the current output data of the sub-block will be written into the corresponding unit of the next sub-block in the next clock. After 256 cycles, the data of the sub-block is moved to the next sub-block as a whole.

2.2 Filter coefficient storage module

The filter coefficient storage module corresponds to the input sequence buffer module and is implemented using a dual-port RAM module. There are a total of four 256-depth dual-port RAM modules, as shown in FIG3 .

Figure 3 Filter coefficient storage module implementation block diagram

The four sub-blocks use the same input data line, and generate the write enable 'wen1~wen4 and write address h_addr of each sub-block through decoding of the coefficient write address, and control the input coefficients to be stored in RAM in sequence. The read address h_addr of the coefficient is generated by the control module, and the four sub-blocks share a read address, and output the coefficients h1~h4 corresponding to the data to the multiplication and accumulation module for multiplication and accumulation operation.

2.3 Control Module

The control module generates a read and write address and an enable signal of the input sequence buffer module and a read address and an enable signal of the filter coefficient storage module, and controls the multiplication and accumulation operation.

The input sequence needs to be repeatedly shifted and output in the cache module for calculation. One number is input every 256 clock cycles, and the write address of the input sequence must lag behind the read address by one clock cycle to ensure data continuity and no loss. In this way, the newly written data is not in a fixed position, which requires that the read address is not a simple cumulative relationship. Take the example of each RAM block depth equal to 4 to study the relationship between the read and write addresses, as shown in Figure 4.

Figure 4 Read and write sequence when each RAM block is 4 deep

It can be seen that the read address order of the input sequence at this time is as shown in FIG. 5 .

Figure 5 Read address when each RAM block is 4 deep

By analogy, the actual read address of the input sequence buffer module is shown in FIG6 .

Figure 6 Input sequence buffer module read address

The implementation of the entire control module is shown in Figure 7. The main counter counts as a whole. Every 256 clock cycles, the address generation module adds 1 to the counter's count value as a whole and outputs it as the read address raddr of the input sequence, realizing the address sequence shown in Figure 6. The write address waddr is obtained by delaying the read address raddr by one clock cycle. Since the input sequence is output in time sequence, the filter coefficients only need to be output in sequence from the storage array accordingly, and the count value of the main counter is directly derived as the read address h_addr of the filter coefficient array.

Figure 7 Implementation of the entire control module

The output of the main counter passes through the decoding circuit and outputs the low-speed sampling clock sa_clk of the data to synchronize the input sequence. It also outputs the write enable wren of the input sequence, which is enabled once every 256 clock cycles and writes data once.

2.4 Multiplication and Accumulation Module

The multiplication and accumulation module is responsible for performing multiplication and accumulation operations on the input data and coefficients, and outputs a filtering result every 256 clock cycles. Its implementation block diagram is shown in Figure 8.

Figure 8: Implementation diagram of the multiplication and accumulation module

The data y1~y4 output by the input sequence buffer module and the corresponding coefficients h1~h4 output by the filter coefficient storage array are multiplied and accumulated in this module. Every 256 clock cycles, the four parts y1'~y4' of one sampling point data are calculated, latched by the latch, and the final filtering result y is obtained after passing through the two-stage pipeline adder. Then the accumulator is cleared to prepare for the calculation of the next sampling point data. Among them, the latch clock of the latch and the clear signal of the multiplication and accumulator are obtained by the write enable wren of the input sequence after the corresponding delay processing.

3 Simulation Results

The designed equalizing filter is synthesized and compiled, and the compilation report is shown in Figure 9.

Figure 9 Compilation report

It can be seen that the 1024-order FIR equalization filter can be implemented in the EP1C3 series FPGA, occupying only about 70% of its logic resources and about 50% of its storage space. In order to verify the design function, the filter coefficients are initialized using the memory initialization file, and the stored coefficients are shown in Figure 10.

Figure 10 Filter initialization coefficients

For intuitive verification, the input sequence x is taken as a δ sequence, that is, only one data in x is 1 and the others are 0. According to the relevant knowledge of filters and convolution, the output result y=x*h=δ*h=h, which is the filter coefficient. The simulation results are shown in Figure 11.

Figure 11 Filter simulation results

The input sequence x has only one sampling clock cycle with data 1, and the rest are all 0. fout is the output filtering result. It can be seen that the result is repeated data from -1 to -16, which is consistent with the filter coefficients shown in Figure 10, and the filter works normally.

4 Conclusion

A 1024-order FIR digital filter was designed using about 70% of the logic units and about 50% of the storage space of EP1C3. By overloading the coefficients, the equalization characteristics of various frequency responses can be achieved, realizing the function of a simple digital equalization filter and achieving the design goal.