A digital self-calibration algorithm for 14-bit SAR ADC

The successive approximation ADC is a common structure for medium- and high-resolution applications with a sampling rate of less than 5 MS/s. The resolution of SAR ADC is generally 8 to 16 bits. It has the characteristics of low power consumption and small size, so it has a wide range of applications, such as portable battery-powered instruments, industrial control and data/signal collectors [1].
Under the current process level, due to the limitations of factors such as capacitor mismatch, system offset and noise, the maximum accuracy that can be achieved by SAR ADC using charge redistribution structure is limited to about 12 bits [2]. Therefore, the design of high-precision ADC must rely on calibration technology. There are two general calibration technologies: analog calibration technology is to adjust the relevant quantity to the normal value in the analog field or use laser to correct the chip components, but this technology is expensive and easily affected by mechanical stress during packaging; there is also a digital calibration technology, which describes the effects of mismatch errors in the circuit in the digital field, and then adjusts the output code in the digital field without caring about the physical quantity value in the analog field [3]. Digital calibration is the mainstream of current calibration technology.
A digital calibration algorithm based on binary weighted capacitor array DAC is proposed. A low-precision DAC is used to represent the mismatch error value of each capacitor to be calibrated. Then, during the AD conversion process, the corresponding error voltage is loaded into the capacitor array to calibrate the capacitor network.
1 SAR ADC core principle
The basic structure of SAR ADC consists of a comparator, DAC, and SAR logic control circuit, as shown in Figure 1.

Basic working process: First, the analog input Vin is sampled and held, and sent to one end of the comparator. The initial value of the N-bit SAR register is the middle value (i.e. 100...00), and the DAC converts this value into the corresponding analog quantity VDAC=VREF/2 (VREF is the reference voltage of the ADC). The comparator starts to compare the size of Vin and VDAC. If Vin>VDAC, the comparator outputs 1, the highest bit of the SAR register is maintained, and the second highest bit is preset to 1; conversely, the comparator outputs 0, the highest bit of the SAR register is 0, the second highest bit is preset to 1, and the ADC performs the next comparison. This comparison is repeated until the lowest bit of the SAR register, and the N-bit digital quantity stored in the register is the conversion result of the ADC.
2 Digital calibration algorithm
The basic idea of ​​the digital calibration algorithm is to calculate some nonlinear errors such as capacitor mismatch before the ADC is used normally, and describe the errors in the digital field in the form of calibration codes accordingly, and load these calibration codes into the circuit for error calibration during normal operation, so as to achieve the purpose of calibrating the mismatch. There are different algorithms for generating and using calibration codes [4, 5]. This paper designs an idea of ​​calibrating capacitors from low to high positions in sequence.
2.1 Algorithm principle of calibration code generation
A symmetrical segmented capacitor structure is used in this design, as shown in Figure 2. The symmetrical differential structure makes the comparator input load equal, eliminates the common mode noise of the comparator, and improves the signal-to-noise ratio; the segmented capacitor array uses a structure in which the high and low positions are coupled through transition capacitors, ensuring the high accuracy of the MSB and the monotonicity of the LSB. The N (N=M+K)-bit SAR ADC consists of a high M-bit DAC with a left and right differential structure and a low K-bit DAC on the left side, and the low K-bit on the right side is used to calibrate the mismatch error of the capacitor array.

During the process of generating the calibration code, two capacitor array working states are set: in the Φ1 working state, a group of capacitors are connected, and the outputs of the left and right capacitor arrays are disconnected from the input of the comparator (the inputs at both ends of the comparator are 0), and the output of the capacitor array is connected to the common mode level VCM; in the Φ2 working state, another group of capacitors is connected, and the output is connected to the input of the comparator for comparison. By switching between the two working sequences, according to the principles of charge conservation and charge redistribution, the mismatch error between the capacitors to be calibrated can be represented by the calibration capacitor array of the low K position on the right.
The following takes the high-position capacitor as an example to analyze the details of the calibration code generation principle. Figure 3 is an equivalent model of the left capacitor array in two different working states.

In Figure 3, CLN represents the sum of all capacitors in the left capacitor array except C1 and C2, C1 represents the sum of all calibrated capacitors, C2 represents the capacitor currently to be calibrated, and C1 and C2 are two adjacent groups of capacitors. Let CT represent the total capacitance value of the left capacitor array, that is, CLN+C1+C2=CT. The VL terminal is connected to one input terminal of the comparator. According to the charge conservation principle under the two working states of Φ1 and Φ2, we have:

In formula (4), C1 is a calibrated capacitor, and there is a weight relationship between C2 and C1, and the mismatch error between C2 and C1 can be described by CV. The value of CV corresponds to the switch binary value of the low-K capacitor array on the right, that is, the influence of the capacitor mismatch error is described in the digital domain, and in the normal conversion process, these errors are loaded in the circuit after corresponding processing to achieve the effect of calibrating the error.
2.2 Implementation of SAR ADC calibration algorithm
Assuming that the mismatch error of the unit capacitor is? resident, the statistical distribution of the high-bit capacitor error can be approximately simulated by adding the number of corresponding bit capacitors. When the statistical error of each bit capacitor and its corresponding weight (2n) product exceeds the unit weight, it is necessary to consider calibrating this bit.
Now assume that the lowest bit capacitor CL1 to be calibrated is a capacitor in the low-K capacitor array on the left. The capacitor C0 one bit lower than CL1 is regarded as the reference capacitor value, and the high-bit capacitors need to be calibrated to 2i×C0 in turn to achieve a mutual matching relationship. First, the size of the reference capacitor C0 needs to be represented by the low-bit calibration capacitor array on the right. In the Φ1 working state, no capacitor is connected to the left and right capacitor arrays, and the output is connected to the common mode level. In the Φ2 working state, the left capacitor array is connected to C0, and the right low-bit calibration capacitor array is connected to the variable Cv0 capacitor. Observe the output of the comparator. When the comparator output jumps, there is:

The Calib collection stores the calibration code value of the corresponding bit capacitor. In the normal SAR ADC analog-to-digital conversion process, it is loaded into the right low-bit calibration capacitor array. Under the joint action of the corresponding capacitor to be calibrated, it plays the role of calibrating the capacitor mismatch error.
3 System behavior level simulation and result analysis
Set the mismatch error of the unit capacitor to 0.5%, and establish a 14-bit capacitor array model with statistical distribution mismatch error. Since the system behavior level simulation this time is to verify the correctness and effectiveness of the calibration algorithm, the comparator is designed to be an ideal comparator that can achieve infinite precision comparison.
The system-level simulation includes the simulation of conventional static parameters such as differential nonlinearity (DNL) and integral nonlinearity (INL) using the code density histogram method, and the simulation of dynamic parameters such as signal-to-noise ratio, signal-to-noise distortion ratio and effective number of bits using the FFT method for spectrum analysis [6].
When simulating static parameters, the accuracy of 0.3LSB and the confidence level of 95% are met, and the number of simulation points is set to 220.
For the spectrum analysis of the ADC, the sampling frequency fs is set to 200 kHz, the number of sampling points N is 8192 points, and the number of sampling cycles M is 129.

When the SAR ADC is not digitally calibrated, the mismatch error between capacitors causes ADC nonlinearity, resulting in spectrum distortion, obvious harmonics on the spectrum, and low signal-to-noise ratio and effective number of bits. From the simulation results (see Figure 5 and Figure 6), it can be seen that the signal-to-noise-distortion ratio SNDR is 72.9 dB, and the effective number of bits is only 11.82 bits. The static parameters INL and DNL are 2.86 LSB and 5.01 LSB respectively, indicating that there is serious missing code.

Under the same sampling frequency and input signal, the SAR ADC is digitally calibrated. From the simulation results (see Figure 7 and Figure 8), it can be seen that after calibration, the nonlinearity of the ADC has been significantly improved, the SNDR has been significantly improved to 85.1 dB, and the effective number of bits is 13.85 bits, which is close to the ideal number of conversion bits. The static parameters INL and DNL are 0.25 LSB and 0.26 LSB respectively.

This paper introduces a digital calibration algorithm based on binary weighted capacitor array SAR ADC in detail. The algorithm uses the charge conservation and charge redistribution principle of the capacitor array under two different working states to achieve the purpose of calibrating the capacitors from low to high bits in sequence, greatly improving the nonlinearity of the overall SAR ADC caused by capacitor mismatch. Through the simulation of the actual 14-bit SAR ADC system level, it can be seen that after adding the calibration algorithm, the signal-to-noise ratio and effective number of bits of the ADC are significantly improved, and the nonlinear distortion is largely suppressed, which verifies the correctness and effectiveness of the calibration algorithm and provides an effective and easy-to-implement digital calibration algorithm for the design of high-precision SAR ADC.
References
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