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[Project Source Code] Summary of Common Knowledge Points of Custom IP in NIOS II SOPC System [Copy link]

 

This article and design code were written by FPGA enthusiast Xiao Meige. Without the author's permission, this article is only allowed to be copied and reproduced on online forums, and the original author must be indicated when reprinting.


Package IP
1. Add the written Verilog code to the Quartus project, under the IP directory (if there is no such directory, create one yourself)
2. Open the Qsys tool and select New Component
3. Enter a reasonable IP name for name and Display name, enter the IP group name or select a reasonable group
4. When adding files, add all files used by this IP, select the top-level file of the IP, set it as the top level, and perform analysis and synthesis
5. All Avalon Slave bus signals are unified in one interface group, and all exported signals are unified in one group The
clock input signal interface is: Clock input clkThe
clock output signal interface is: Clock output clkThe
reset input signal interface is: Reset input reset/reset_nThe
reset output signal interface is: Reset output reset/reset_nThe
export signal unified interface is: conduit_end Select export for signal type The
Avalon bus unified interface is: as/ avalon slave Select the corresponding signal type according to the actual meaning of the signal
The interrupt request signal interface is: interrupt sender Select irq or irq_n for signal type
6. In the Interface tab, remove the meaningless signal groups through the Remove Interface whit No Signals option
7. Assign clock and reset to each group of signals
8. Bind the interrupt group to the Avalon bus
9. According to actual needs, set the time parameters in the timing column
10. Finish save to save the settings. These settings are saved in a tcl file with the IP name plus hw, such as ADC_hw.tcl
11. Since the tcl file is not placed in the same place as the IP source file, it is not convenient to analyze and reuse. So move the tcl file to the IP source file directory and then use Notepad to delete all the relative path description information, leaving only the file name.

This post is from Altera SoC
 
 

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