How to Enable the ITU-T G.703 2048kHz Synchronous Interface in the DS26303 LIU

A little-known feature of the DS26303 E1/T1/J1 octal line interface unit (LIU) is its ability to transmit and receive 2048kHz synchronous interface (T12) signals in accordance with clause 13 of ITU-T Recommendation G.703 (November 2001). This application note describes how to properly program the DS26303 to enable the 2048kHz synchronous interface mode for clock distribution applications such as integrated timing supply systems (BITS) or timing supply units (SSUs). It should be noted that there are two DS26303 products available: the DS26303-120 and the DS26303-75. The only difference between the two is the default E1 line impedance setting. This feature must be noted to ensure that the same device is used during the design and production phases.

The DS26303 is set to work in 2048kHz synchronous interface mode

Programming the DS26303 to support a 2048kHz synchronous interface is a multi-step process that uses some registers that are not listed in the DS26303 data sheet. A description of all the registers that are not listed is provided in the Appendix.

Before enabling the 2048kHz synchronous interface mode, it is necessary to perform some configuration operations to ensure that the DS26303 operates according to the required procedures.

The first step is to change the internal clock to use the transmit clock corresponding to the LIU channel (usually the TCLK input) instead of the master clock (MCLK input). By default, when the 2048kHz synchronous interface mode is enabled, the DS26303 uses the common MCLK input as the clock source. This causes the output signal of the TTIP/TRING pin to be frequency locked to the MCLK input instead of the TCLK input. The following software configuration can be used to program the DS26303 to use the TCLK input as the clock source.

Set the ADDP register at address 0x1F to 0x03 to select the global test register group.

Set the TXDIG register at address 0x07 to 0x10. By setting bit 4 of the TXDIG register to 1, the 2048kHz synchronous interface mode will use the TCLK input instead of the MCLK input. It is important to note that changing bit 4 of the TXDIG register affects the other two functions that use the MCLK input as the clock source, namely, the Transmit All 1s (TAOE) and Automatic Transmit All 1s (ATAOS) functions. Therefore, this bit needs to be set to 0 after disabling the 2048kHz synchronous interface mode. However, if the designer wants to use the TCLK input as the clock source after enabling TAOE or ATAOS, bit 4 of the TXDIG register can be set to 1.

The second step is to change the current limit of the short-circuit detection circuit (SCDC) to prevent the TTIP/TRING transmitter output from shutting down. By default, the DS26303 current limit is incorrect when the 2048kHz synchronous interface mode is enabled. To set the DS26303 with the correct short-circuit current, the following software configuration is required.

Setting the ADDP register at address 0x1F to 0x04 to 0x0B will select the LIU1 test to LIU8 test register groups respectively.

Set the TXCMDA register at address 0x05 to one of the following values ​​(Table 1), which should be synchronized with the values ​​of the template select (TS) register. For example, if the TS register is configured for E1 75Ω mode, set the TXCMDA register to 0x33. In addition, the transmit impedance termination of the TS register should not be turned off after enabling the G.703 2048kHz synchronous interface mode. Note that bits 7:6 of the TXCMDA register should always remain 0; bit 5 controls the SCDC control enable; bits 4:0 contain the new short-circuit current threshold. Although the threshold can be adjusted, it is not recommended because these values ​​are selected to prevent device damage.

Table 1. TXCMDA register settings

After completing the above two configuration steps, the DS26303 is correctly configured to support 2048kHz synchronous interface mode.

To set up one or more channels of the DS26303 to support 2048kHz synchronous interface mode, follow the software configuration described below.

Set the ADDP register at address 0x1F to 0x01 to select the independent LIU register set.

Set the G703EN register at Address 0x08 to the required value to enable the 2048kHz synchronous interface mode for the appropriate LIU channel.

Assuming the TTIP/TRING transmit output has been disabled as recommended above, the transmitter output is enabled via the following software configuration.

Set the ADDP register at address 0x1F to 0x00 to select the primary register bank.

Set the OEB register at Address 0x12 to the required value to enable the TTIP/TRING transmitter output for the same LIU channels enabled by the G703EN register.

in conclusion

The default values ​​of the DS26303 have been changed to fully support the ITU-T G.703 2048kHz Synchronous Interface (T12) specification. This application note describes the necessary changes, as well as background information and a detailed configuration procedure. With this information and the DS26303 data sheet, designers can integrate the 2048kHz synchronous interface functionality into a BITS or SSU design.

Appendix: DS26303 Register Information

The register space address of DS26303 is 0x00 to 0x1F, using the storage zone mode, which contains the configuration and status information of all LIU channels. The ADDP register at address 0x1F is a special register that stores pointers to access different register groups. For each specified register group, the function and value of this register remain unchanged. However, changes to the ADDP register will change the current register group, thereby changing the function and value of the registers at addresses 0x00 to 0x1E.