White LED Charge Pump Board Layout Guidelines

For the MAX1576 white LED charge pump, the following rules need to be followed in the circuit board layout:

Connect all GND and PGND pins directly to the exposed pad (EP) under the IC.

The input, output and flying capacitors are preferably ceramic capacitors with X5R electrolyte or better. Low ESR is critical for high current output, low input/output ripple and stability.

To avoid switching noise from the IC bias circuit, the input capacitors (CIN and CINP) need to be placed as close to the input and ground pins as possible, preferably with no vias between the capacitors and the IC.

Figure 1

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If there are separate GND and PGND and/or IN and PIN pins, the IC contains separate power and bias inputs. If these pins are not close together, two input capacitors are required: CINP from PIN to PGND and CIN from IN to GND, each capacitor should be placed as close to the IC as possible. In this case, PIN and PGND should be connected to the system power and ground plane respectively, while IN and GND are connected nearby. The PCB power lines first enter CINP and INP, and then connect to CIN and IN through some vias, providing some input noise filtering at the IN end. PGND and GND should be connected together through the exposed pad.

To ensure stable operation of the charge pump, place the output capacitor, COUT, as close to the OUT pin as possible. Connect the ground terminal of COUT to the nearest PGND or GND pin, or the exposed pad (EP).

To ensure the ground output impedance of the charge pump, the flying capacitors (C1 and C2) should be mounted as close to the IC as possible. If vias cannot be avoided, it is best to connect them in series with C1 and/or C2 rather than with CIN or CINP, because the flying capacitors have no effect on the stability of the device.

The ground end of any reference bypass capacitor (not available on the MAX1576) or the ground end of the setting resistor (RM and RF on the MAX1576) should be connected to the GND pin (as opposed to PGND). This helps reduce noise coupling into the analog circuitry of the IC.

The exposed pad (EP) can optionally use large vias to facilitate inspection of the solder joint and to facilitate removal of the IC from the PCB with a soldering iron.

The logic inputs can be routed as needed to connect to the LEDs. Vias on these leads will not cause any problems because the current at these outputs is stable. However, be careful if these leads are close to sensitive RF circuits, as ripple on the leads may affect the RF circuits.