Design of high performance PHS RF transceiver chip

　　With the expansion of PHS protocol, PHS has continuously introduced new highlights in system and services, such as seamless switching, machine-card separation and QBOX smart wireless service. The introduction of these new services will become a powerful driving force for the future development of PHS . In response to the new technology requirements of PHS system for mobile phones, RDA Microelectronics has developed a single-chip transceiver based on a new RF transceiver structure and a high-efficiency power amplifier module with integrated antenna switch. This article introduces the design method of RDA PHS RF transceiver chip.

　　In China, PHS, as a supplement and extension of the fixed telephone network, has become a weapon for fixed network operators to quickly seize the market with its low charging model in the early stage of development. With the expansion of the PHS protocol, PHS terminals can not only realize all the functions of fixed telephones, but also support functions including call transfer, multi-party calls, voice mailboxes, etc. At the same time, it also has some functions of mobile phones, such as cross-region roaming, wireless Internet access, positioning and ISDN services. In addition, PHS has continuously introduced new highlights in systems and services, such as seamless switching, machine-card separation and QBOX Lingtong cordless services. The introduction of these new services is bound to become the driving force for the future development of PHS.

　　The target market of the PHS system is mainly low-end and mid-range customers, and the price sensitivity of end users to PHS phones is much higher than that of GSM and CDMA systems. With the intensified competition among GSM, CDMA and other systems in the communication market, and the new 3G system approaching step by step, the production cost of PHS phones has become more sensitive to PHS phone manufacturers and operators.

　　RDA Microelectronics PHS Mobile Phone RF Front-end Solution

　　However, the opposite is true in the case of PHS mobile phone solutions. Although the PHS system has been in operation for ten years, due to its failure in the Japanese market, Japanese manufacturers that provide terminal chip solutions have long stopped optimizing and improving the design of terminal solution chips. This situation is more prominent for RF front-end transceivers. The existing transceiver chips have obvious technical disadvantages in terms of integration because they use the traditional double-frequency conversion transceiver structure in the system structure. This has become the main obstacle for PHS mobile phone manufacturers to develop new models and reduce the cost of the whole machine.

　　As the PHS system continues to improve, system manufacturers have also put forward more stringent requirements for the indicators of RF transceivers, many of which are far higher than the protocol requirements. For example, in QBOX applications, the distance between the main machine and the sub-machine may be very close, which results in a large input signal power. Therefore, the receiver is required to have a high linearity to ensure that the circuits at all levels do not have nonlinear distortion. In addition, due to the large dynamic range of the input signal of the PHS mobile phone, the AGC circuit must be used to keep the signal at the baseband interface basically constant. In order to reduce the AGC stabilization time, and the traditional PHS baseband chip does not directly perform power detection, the AGC loop must be fully integrated at the receiver end and provide RSSI to the baseband. In addition, in order to meet the requirements of seamless transit switching of mobile phones, the PLL must have an extremely fast locking time, which is only equivalent to 1/8 of the similar indicators of the GSM system.

　　For this purpose, RDA Microelectronics has developed and designed a PHS RF chipset, which consists of two chips: the RF transceiver chip (RDA5205) and the power amplifier/switch module (RDA5212), forming a complete PHS mobile phone RF front-end solution. Among them, the transceiver chip RDA5205 is a fully integrated single-chip PHS transceiver. Due to the use of an advanced near-zero intermediate frequency (LOW-IF) receiving structure and the integration of the PLL circuit including the VCO and loop filter on the chip, it has the characteristics of high integration, few peripheral components and easy use. The RDA5212 power amplifier/switch module has good out-of-band suppression in system applications, and the antenna and the power amplifier output do not require the RF surface acoustic wave filter (SAW) required in traditional solutions.

　　In addition to RDA5205 and RDA5212, the overall RF solution only requires a single-ended to dual-ended RF filter, a TCXO, an LDO, and a small number of peripheral RC components. Such a high level of integration makes the number of peripheral components of the RDA PHS RF solution only 1/5 of that of the traditional solution, and the PCB area is equivalent to 1/3 to 1/4 of the traditional solution. While reducing the cost of PHS mobile phones, the RDA PHS RF chipset ensures the requirements of new RF indicators such as seamless switching of the new version of PHS mobile phones, making mobile phone products using this RF chipset extremely cost-effective and greatly improving the market competitiveness of terminal products.

　　The main components of RDA Microelectronics PHS mobile phone RF front end are as follows:

　　(1) Receiving link

　　The receiver adopts a near-zero IF architecture. This architecture avoids the problems of the superheterodyne architecture, such as the need for an off-chip SAW filter, high cost, and difficulty in monolithic integration, and also avoids the problems of the zero IF architecture, such as DC offset and 1/f noise. It can be said that the near-zero IF architecture avoids the shortcomings of the above two architectures, while inheriting the advantages of the superheterodyne architecture, such as excellent performance, and the zero IF architecture, which is suitable for monolithic integration.

　　The antenna receives the signal, passes through the switch and the single-turn dual RF filter, and filters out some of the out-of-band interference. Then it is amplified by the LNA, and the mixer is orthogonally down-converted (low LO) to a center frequency of half the channel bandwidth (i.e. 150kHz). The selection of this intermediate frequency is mainly based on the consideration that its image channel (+300kHz) is "clean", that is, the two adjacent channels on the left and right of the useful channel in the PHS system will not be allocated. In addition, the circuit adopts low-noise technology, which greatly reduces the 1/f corner frequency and reduces the impact on SNR. The down-converted signal is complex filtered to further filter out the out-of-band interference and perform partial channel selection. The PGA amplifies the signal amplitude to a suitable value under the control of the AGC, and leaves enough space for the ADC to accommodate strong blockers and attenuation outside the channel. The red box part in the figure represents the DSP, which first down-converts the signal to the baseband and then performs channel selection filtering. The processed signal is converted into an analog baseband IQ signal through the DAC. RDA5205 provides three receiving baseband interfaces: the first is to up-convert the analog baseband signal to 10.8MHz IF, which is used by traditional basebands; the second is the analog baseband interface; the third is the 150kHz baseband interface. The latter two interfaces mainly meet the requirements of the new generation of PHS basebands.

　　(2) Transmitting link

　　The transmitter uses a direct up-conversion architecture. The baseband IQ signal first passes through a low-pass filter to constrain the channel spectrum, and then is orthogonally up-converted to the RF. The RF VGA provides a 60dB dynamic range and a resolution of 0.5dB/step. The signal is then amplified by the PA driver and converted from double-ended to single-ended, and then drives the PA. The final signal passes through the switch and is transmitted by the antenna.

　　(3) Frequency synthesizer

　　The frequency synthesizer uses fractional N PLL. The reference frequency is equal to the TCXO frequency, that is, 19.2MHz. The loop filter can select a relatively high bandwidth to reduce the stabilization time, thereby meeting the requirements of seamless switching of the system. Since the PLL uses a new technology independently developed by RDA, all PLL circuits including the loop filter can be integrated on the chip.

　　Baseband control: The baseband controls the transceiver chip, power amplifier and switch through a standard 3-wire system. Various controls include: initial setup, automatic calibration, working state switching, setting PLL frequency and TX APC control, etc.

　　RDA5205 is implemented by SMIC 0.18um 1P5M CMOS process, using standard QFN package, the package size is only 6×6mm. For RF chip design, CMOS process has a price advantage over BiCMOS process. RDA has been committed to the research of CMOS technology. Due to the use of new circuit technology and isolation technology, CMOS transceiver chip is not inferior to similar BiCMOS chip in terms of low noise, digital-analog mixing, anti-crosstalk and other aspects.