2.45GHz WLAN Power Amplifier Design

　　1 Introduction

　　In recent years, with the rapid development of wireless communication technology, the demand for fully integrated, high-performance, low-cost wireless transceivers has become increasingly urgent. A key module in the transmitter system is the power amplifier. From the perspective of power consumption, the power loss of the power amplifier accounts for a large proportion of the total power consumption of the transmitter. Therefore, the design of a high-efficiency CMOS power amplifier is particularly important. With the continuous development of RF CMOS technology, the performance of RF integrated circuits based on Si CMOS technology has been greatly improved in the GHz frequency band. It has the characteristics of high integration, low power consumption and low cost, and can be compatible with baseband digital circuits. Finally, system-on-chip integration (SOC) can be achieved. Therefore, in recent years, the research on Si CMOS RF integrated circuits has become a hot topic in international research.

　　Power amplifiers are usually divided into two categories: linear and nonlinear. There are four types of linear amplifiers: A, B, AB and C. The main difference between them is the different gate bias conditions. This type of traditional power amplifier has high linearity but low efficiency; nonlinear amplifiers mainly include D, E and F. For the wireless LAN in this article, high linearity is required. Therefore, the two stages use A and AB amplification modes respectively.

　　2 Power amplifier circuit design

　　A typical power amplifier generally includes an input matching network, a transistor amplification circuit, an inter-stage matching network, a bias network and an output impedance matching network, as shown in Figure 1 below.

　　Figure 1 Power amplifier block diagram

　　2.1 Self-biased Cascode Structure

　　For power amplifiers, the maximum power supply voltage between the drain and gate of a standard 0.18um CMOS process transistor is 2V, and the breakdown voltage is about 4V. In a power amplifier, the sum of the DC and AC voltages at the drain end of the tube can reach 2-3 times the power supply voltage, which poses a risk of breakdown to the gate oxide layer of the tube. When designing a PA, the maximum voltage Vmax that a transistor can withstand is limited by the breakdown voltage of the transistor, while the minimum voltage is limited by the Knee voltage. The use of a Cascode structure in a power amplifier can alleviate the pressure of transistor breakdown and increase the swing of the power amplifier output voltage, thereby reducing the requirements for the maximum current capability of the transistor, improving the efficiency of the power amplifier, and reducing the size of the output transistor. In fact, in a common-source common-gate amplifier, the common-gate transistor is the bottleneck of voltage breakdown and hot carrier effects.

　　Therefore, this paper adopts the Cascode self-biased structure and thick gate devices, which can not only improve the low breakdown voltage of deep submicron CMOS devices, but also reduce the influence of hot carrier effects. In the traditional Cascode amplifier shown in Figure 3, the gate-drain voltage waveform of M2, Vg2 is always fixed at 3V, and the positive peak voltage of Vd2 is 4.8V, so the gate-drain voltage difference is 1.8V. In order to overcome this problem, Figure 4 shows a self-biased Cascode structure amplifier circuit, which introduces the AC voltage Vd2 of the drain end of the M2 tube to the gate end Vg2, so that when we design the power amplifier, the two MOS tubes have the same maximum drain-gate voltage as much as possible. Therefore, before the hot carrier effect appears, the M2 tube has a large signal swing. The bias of G2 is achieved through Rb-Cb. Figure 6 shows the voltage waveform of Vd2 to Vg2 of the M2 tube, and its maximum voltage difference is 1.4V. Compared with the traditional circuit, it is reduced by 0.4V, so the voltage difference of Vdg of the self-biased M2 tube is reduced by 23% compared with the M2 tube of the traditional structure.

　　Figure 2 Traditional Cascode Amplifier

　　Figure 3 Gate-drain voltage waveform of M2 in a traditional cascode amplifier

　　Figure 4 Self-biased cascode amplifier

　　Figure 5 Equivalent circuit diagram of self-biased cascode amplifier

　　According to the equivalent circuit diagram above, we can get two

The expression is:

(1)

(2)

　　Similarly, we can also get two

The expression is:

　　(3)

(4)

　　Substituting equation (2) into equation (3) and equation (4) and making them equal, we can obtain the following gain expression:

(5)

(6)

(7)

(8)

　　From the gain expression of formula (8), it can be seen that if Rb or cb increases, the gain of the amplifier will increase. However, from the voltage waveform after circuit simulation, it can be seen that if Rb or cb increases, the voltage swing of Vg2 will decrease, so the voltage waveform of the drain node will begin to distort when the input power is low. Therefore, the value of Rb or cb should not only be determined based on the gate-drain signal swing of M1 and M2 tubes as close as possible, but also strive to find a good compromise between gain and linearity.

　　Figure 6 Gate-drain voltage waveform of M2 in self-biased cascode amplifier

　　2.2 Design and simulation of power amplifier

　　For the wireless LAN application in this article, since non-constant envelope modulation is used, high linearity is required, so the first stage of this power amplifier works in Class A and the second stage works in Class AB. Class A amplification mode can provide better linearity, while Class AB amplification mode has higher efficiency than Class A amplification mode. Therefore, the power amplifier in this article has made a good compromise between linearity and efficiency.

　　2.2.1 Amplifier circuit design

　　In order to meet the design requirements of the power amplifier, a two-stage amplifier structure is used because a single-stage amplifier cannot achieve the predetermined power gain index at high frequencies. As shown in Figure 7, the first stage adopts a common source and common gate structure, which improves the isolation of the front and rear stage circuits while providing a suitable voltage gain, providing convenient conditions for impedance matching. The second stage adopts a thick gate common source structure to withstand a higher power supply voltage. The main body is divided into the following parts: (1) C1, C2, and L1 are input impedance matching, which is implemented on-chip to match the input end of the circuit with the 50Ω port.

　　L3 is the choke inductor of the first-stage amplifier circuit. Considering the large current flowing through the power amplifier, it is implemented off-chip. (2) M1 and M2 are the driver stage. (3) C5, C6, and L4 are the inter-stage matching network. In addition to matching between the two stages, they can also be used to adjust the gain flatness of the amplifier circuit [5]. (4) M3 is the power stage. (5) C8, C9, and L7 form a ∏-shaped output matching network, which can effectively suppress even-order harmonic components and achieve optimal load matching [6]. In order to reduce losses, the output matching network C8, C9, L7 and the choke inductor L6 are also implemented off-chip. (6) The ground inductance of CMOS has a great influence on the gain and efficiency of the amplifier, so the parasitic effects of the bonding wire and pad are taken into account during circuit simulation. Among them, L2 and L5 are the bonding wire inductances of the multi-PAD.

　　Figure 7 Power amplifier circuit diagram

　　2.2.2 Simulation Results

　　The performance simulation and optimization of the circuit are completed using Agilent's ADS (Advanced Design System) software. The transistors in the amplifier work in the large signal state, and the nonlinear effect is very significant. Therefore, when designing the amplifier circuit, the equivalent model of the small signal circuit is no longer applicable, and the nonlinear characteristics of the transistor must be fully considered. Figure 8 is the simulated output power, gain and PAE curves with input power. It can be seen from the figure that within the signal range where the input power is less than 0dBm, the gain of the power amplifier is 22dB. At the 1dB power gain compression point, the output power is 22dBm, and the corresponding PAE is 30.4%. Figure 9 is a curve of the S11 parameter of the power amplifier with frequency. It can be seen from the figure that S11 is less than -20dB near the center frequency of 2.45GHz, so the input matching basically meets the design requirements.

　　Figure 8 Output power, gain and PAE curves versus input power

　　In addition, other important parameters obtained by simulation are: the output third-order junction point is about 29 dBm; the stability factor K is K>1 within the working frequency band.

　　Figure 9 S11 parameter curve of power amplifier

　　2.2.3 Layout Design

　　Cadence software was used for layout design. The power amplifier uses SMIC 0.18μm CMOS process. The transistors used in the amplifier circuit use RF models. The layout design mainly considers the following issues:

　　(1) Since the current flowing through the power amplifier is very large, several layers of metal are connected in parallel on the power line and the ground line to avoid electromigration. (2) The parasitic inductance of the ground bonding wire seriously affects the power output of each level of the circuit. Therefore, in order to minimize the parasitic inductance of the ground bonding wire, multiple ground pads are set and multiple bonding wires are led to the ground wire. (3) For high-frequency signal lines, try to use the top and upper layers of metal, and it is best to follow the principle of the shortest signal line to reduce losses caused by parasitic capacitance, coupling and other factors.

　　Figure 10 PA layout

　　3 Conclusion

　　A power amplifier working in 2.45GHz WLAN is designed using the SMIC 0.18um CMOS process RF model. Through the application of self-biasing technology, the power amplifier works under a 3V power supply voltage. Its simulation performance indicators show that the maximum output power can reach 24.5dBm, the corresponding PAE reaches 40%, and the power gain is 23dB, which is suitable for wireless LAN 802.11b system applications.