Design of QPSK modulation circuit based on CPLD

　　QPSK is a commonly used multi-level modulation method in digital communication systems. The basic principle of its modulation is: the input binary sequence is divided into a group of two code elements, and they are characterized by four phases of the carrier. In fact, the QPSK signal is a two-way orthogonal double-sideband signal. Nowadays, people have higher and higher requirements for communication, high speed, large capacity, and multiple services, which pose a great challenge to limited spectrum resources. Therefore, the research on phase shift keying is of great significance. Due to the limitations of channel conditions, most digital communication systems use frequency shift keying, phase shift keying and corresponding derivative modulation methods that are insensitive to amplitude fluctuations.

　　Based on the above QPSK modulation, this design uses the phase selection method based on CPLD to achieve modulation.

　　1. QPSK modulation principle

　　The sinusoidal carrier of the QPSK signal has four possible discrete phase states, and each carrier phase carries two binary symbols (00, 01, 10, 11). Its signal expression is as follows: Figure 1(a) is the vector diagram of the QPSK signal with an initial carrier phase of 0°, and Figure 1(b) is the vector diagram of the QPSK signal with an initial phase of 45°.

　　figure 1

　　There are two methods to generate QPSK modulation: the multiplication circuit method and the phase selection method.

　　Multiplication circuit modulation: The binary code is divided into two half-rate bipolar codes through a serial-to-parallel converter. The two signals are low-pass filtered and multiplied with two mutually orthogonal carrier signals respectively. Then the two signals are added to obtain a QPSK signal.

　　Phase selection method: The input binary data is converted from serial to parallel to output a two-bit symbol. The four-phase carrier generator outputs four carriers with different phases. The logic phase selection circuit selects one of the phases of the carrier as the output in each time interval according to the two-bit symbol input from the serial/parallel conversion. The out-of-band interference signal is then filtered out through a bandpass filter to obtain a QPSK modulated signal.

　　2. Modulation principle of this design

　　The phase selection method is used in the design. The QPSK signal has four states (00, 01, 10, 11), and every two bits of the input binary sequence are divided into a group.

　　In the scheme, four waveforms are used to represent four phases (Figure 2)

　　figure 2

　　3. System module design

　　The circuit is divided into 6 parts:

　　Part 1: Power supply circuit, which provides 5V voltage for the whole circuit;

　　Part 2: Clock signal circuit, used to generate a 4MHz clock;

　　Part 3: Baseband signal generation circuit, generates five sequence codes (all 0 code, all 1 code, 0\1 code, 7-bit M sequence and 15-bit M sequence);

　　Part 4: Modulation circuit, which realizes the modulation of baseband signal into sampling signal output;

　　The fifth part: D/A conversion circuit, which converts the signal output by the modulation module into an analog signal output;

　　Part 6: Filter circuit, which reconstructs the analog signal after D/A conversion by filtering. 　　3.1 Power module

　　There are many design implementation schemes to provide 5V voltage for the circuit, such as using USB to provide 5V voltage or designing a DC regulated power supply. The design of a DC regulated power supply requires the use of a power transformer, a rectifier circuit, filtering, and finally voltage stabilization. The design is relatively complicated. In the design, a 9V output power supply is purchased to convert the 9V power supply into a 5V power supply. The circuit consists of a 7805 chip and 2 capacitors. Pin 1 of the 7805 is connected to the power supply voltage input, pin 2 is grounded, and pin 3 outputs a 5V voltage after voltage stabilization. C1 and C2 are used to filter out ripples.

　　3.2 Clock signal module

　　The clock circuit module consists of two inverters to form feedback, and cooperates with one capacitor and two resistors to start the crystal oscillator to generate a 4MHz clock.

　　3.3 Baseband signal generation module

　　The function of this module is to generate five baseband signals (all 0 codes, all 1 codes, 0\1 codes, 7-bit M sequence and 15-bit M sequence).

　　3.4 D/A Module

　　The signal modulated by the modulation module is a digital baseband signal, which needs to be converted into an analog signal through D/A. DAC0832 is selected in the design to realize D/A conversion.

　　The output of DAC0832 is current, but the output is required to be voltage, so the circuit must also be converted into voltage through an operational amplifier.

　　3.5 Filter Module

　　The filter circuit used in the design is a voltage-controlled voltage source low-pass filter. Its cut-off frequency is 50KHz, the gain is 2, and K=5.

　　4. Modulation signal simulation

　　The simulation results of the modulated signal are as follows:

　　When the 0/1 code is input, since the register y is 2, the loop output level is 005A7FBF.FFBF7F5A. The simulation waveform is shown in Figure 3.

　　image 3

　　When a 15-bit M sequence code is input, the output level is not cyclic because the register y value is changing. The simulation waveform is shown in Figure 4.

　　Figure 4

　　5. Conclusion

　　The main hardware modules of this design are baseband signal generation module, modulation module, D/A conversion module and filter module. In order to simplify the design system design, the power supply module adopts 5V battery power supply. The baseband signal generation module and modulation module are the key points and difficulties in the design. It is based on CPLD design. CPLD is a highly integrated logic element. With the characteristics of high integration, it has the advantages of improved performance, increased reliability, reduced PCB area and low cost.