A new input current detection method based on digital power controller UCD3138 (Part 1)

1 Introduction

1.1 Application of digital power controller UCD3138

Digital power controller UCD3138 is usually placed on the secondary side of DC/DC power supply due to its good feedforward function, communication function and programmability. Common topology schemes include full bridge, half bridge and LLC. Figure 1 shows the block diagram of hard switch full bridge system using digital power (controller) UCD3138. UCD3138 is located on the secondary side and transmits the drive signal to the primary side through digital isolator ISO7420CF.

Figure 1. Hard-switching full-bridge system block diagram

1.2 Current Transformer in Isolated Power Topology

Figure 2 shows a current transformer used in full-bridge topologies. Its primary side is connected in series to the main power circuit, and the secondary side multiplies the current information attenuated in proportion (the proportional coefficient is the turns ratio T of the transformer) by the sampling resistor to obtain voltage information. The controller UCD3138 on the secondary side can complete functions such as cycle-by-cycle protection by reading the voltage information.

Output voltage of the secondary side of the transformer: VT = (Iin÷T) × Rs

Figure 2. Current Transformer Application Circuit

1.3 Principle of input current detection

Figure 3 shows the voltage signal at the output end of the secondary side of the current transformer. The upper and lower waveforms are the corresponding outputs when the input voltage is different. After the output power is determined, as the input voltage increases, the rising edge of the trapezoidal wave will become steeper and its average value will become lower.

Figure 3. Current Transformer Output Signal

The average value of the signal at the output end of the current transformer is approximately proportional to the average value of the system input current, so the input current can be inferred by reading the average value of the output end of the current transformer.

2 UCD3138 AFE module and Filter module

2.1 Module Function Overview

The AFE and Filter of UCD3138 are used to complete the acquisition, conversion and loop calculation of the output voltage error. The output data enters the DPWM module and finally generates a suitable duty cycle, as shown in Figure 4.

Figure 4. UCD3138 AFE and Filter

In practical applications, AFE and Filter can be used to collect the signal at the output of the current transformer and finally calculate its average value. The realization of this function depends on the following characteristics of AFE and Filter:

1) The EADC in the AFE has an oversample function and can collect 1, 2, 4, or 8 samples in one cycle;

2) AFE can average the data output by EADC, that is, it can accumulate 2, 4, or 8 consecutively collected data and then divide it by the number to get the average value.

3) The filter is a PID structure, so only the accumulation link (Integration branch) can be used to calculate the cumulative sum over a period of time.

2.2 Oversampling of EADC

The DPWM module can generate a sampling trigger signal in the EADC module, so that the EADC completes one sampling. At the same time, the EADC also has the function of multiple (2 times, 4 times and 8 times) sampling. Taking 8 sampling as an example, when the EADC receives the sampling trigger signal of the DPWM, the EADC completes 8 samplings at 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 and the sampling base, respectively, as shown in Figure 5.

Figure 5. EADC Oversample

2.3 EADC averaging

EADC provides two data averaging methods, namely, continuous mode averaging and spatial mode averaging. Figure 6 shows how to average data in continuous mode. The principle is to accumulate 2, 4 or 8 consecutively sampled data, and then divide it by the accumulated number to get the average value.

The calculated average value will be sent to the Filter stage.

Figure 6. EADC Oversample

2.4 UCD3138 Filter

Figure 7 is the filter of UCD3138, based on PID structure. When only I branch (accumulation link) is used, Xn data can be accumulated continuously, and the accumulated result is stored in KI_YN register. Xn data is the output from EADC.

Figure 7. UCD3138 Filter Structure

2.5 Full-process data processing

When oversample is configured to 8 times and the average number of EADC is configured to 2 times, the data obtained by the KI_YN register within 2 cycles is shown in Figure 8 below:

1) 8 samples are collected in each cycle, so a total of 16 samples are collected in 2 cycles;

2) Every two samples are averaged, and the averaged data enters the accumulation stage;

3) In 2 cycles, the KI_YN register stores the accumulated sum of 8×2=16 samples in total;

Figure 8. Full-process data processing