This article explains the effects of DC bias supplies on operational amplifiers (op amps) used in sensitive analog applications. It also covers power supply sequencing and the effects of DC supplies on input offset voltage. It also shows a method to easily implement tracking split supplies using linear regulators (which typically do not have tracking capabilities) to help minimize some of the adverse effects of DC bias supplies.

In many op amp circuits, the DC bias supply affects the performance of the op amp, especially when used with high-bit count analog-to-digital converters (ADCs) or for signal conditioning in sensitive sensor circuits. The DC bias supply voltage determines the input common-mode voltage of the amplifier, as well as many other specifications.

During power-up, the sequencing of the DC bias supplies must be coordinated to prevent the op amp from latching up. This can destroy, damage, or prevent the op amp from operating properly. This article explains the importance of tracking supplies for op amps and describes a method to easily implement a tracking split supply using linear regulators that do not typically have tracking capabilities.

There are two common ways to power an op amp. The first and simplest method is to use a single positive supply, as shown in Figure 1 (a). The second method is to use a split (dual) supply, as shown in Figure 1 (b), which has both a positive and a negative voltage. This split supply is very useful in many analog circuits because it allows input signals to include zero voltage potential or input signals that swing between positive and negative.

Figure 1. Op amp power supply options

Regardless of which method is used, the input common-mode voltage is determined by the supply voltage. The input common-mode voltage is simply the arithmetic mean of the two voltages. Equation 1 can be used to calculate the input common-mode voltage, where VP is the value of the positive voltage rail and VN is the value of the negative voltage rail.

For a single-supply system, VN is always zero because the negative rail of the op amp is connected to ground potential.

Equation 1

Using the values ​​shown in Figure 1, the single-supply op amp has an input common-mode voltage of 7.5V, while the split-supply op amp has an input common-mode voltage of 0V.

Some op amps can operate in either a single-supply configuration or a split-supply configuration. Some op amps can even operate with asymmetrical split supplies (VP ​​is not the same size as VN). In all cases, the designer needs to verify that the op amp can support the desired power configuration.

Additionally, many op amps feature split supplies, so if an op amp is designed for split-supply operation in a single-supply configuration, there may be some performance differences.

When using symmetrical split supplies, the positive and negative voltages must track each other, especially when the circuit is first powered up. A tracking supply is a power supply that regulates its output voltage to another voltage or signal. For most op amps, the positive supply voltage should always be equal and opposite to the negative supply voltage.

Alternatively, you can adjust the negative supply to be equal in magnitude and opposite in polarity to the positive supply. Either method will produce the same power-up waveform.

The op amp can latch up during power-up if the two supplies are not equal in magnitude and opposite in polarity. Latch-up can destroy, damage, or prevent the op amp from operating properly.

Figure 2 shows a schematic diagram of a typical op amp power supply circuit. Here, a switching power supply provides a positive 18V and a negative 18V. Two low dropout (LDO) linear regulators further regulate the ±18V to ±15V. The LDO is typically installed between the power supply and the op amp to reduce the high-frequency switching noise generated by the switching power supply. The LDO has a high power supply rejection (expressed as a ratio, PSRR), which attenuates the noise at the LDO input over a wide frequency bandwidth.

Figure 2 Typical power supply structure of an operational amplifier (click on the image to enlarge)

This helps provide a low noise power supply to the op amp. The op amp also has its own PSRR, which is typically above 80dB. However, the op amp only has a high PSRR over a few kilohertz bandwidth, so the LDO is used to provide a high PSRR up to hundreds of kilohertz bandwidth.

The circuit shown in Figure 2 has no inherent tracking capability. During power-up, there is no guarantee that each LDO will be equal in magnitude and opposite in polarity to the other LDO. During power-up, the output voltage of each LDO is determined by all the soft-start circuitry, current limiting, load capacitance, load current, and input voltage.

Therefore, it is possible for the two voltages to be different in magnitude and polarity at startup. Also, after the LDO is powered up and providing a steady-state DC output, they may still be unequal in magnitude because each LDO has its own output voltage accuracy and the feedback resistors may vary slightly due to their tolerances.

In addition to latch-up issues during power-up, each power supply can have an impact on system performance if its final operating DC voltage varies over time. Power supply output will vary with line voltage, load current variations, and temperature variations. Power supply output will vary within its accuracy specification, which is typically 3% to 5% of the rated output voltage.

Although these changes in supply voltages are small, they change the op amp's input common-mode voltage point, which is usually modeled as an additional compensation voltage at the op amp input. Because op amps have high PSRR, the modeled compensation voltage is equal to the input common-mode voltage change divided by the op amp's PSRR. Equation 2 can be used to calculate the compensation voltage at the op amp input due to supply changes.

Equation 2

The PSRR is expressed in decibels as shown in Equation 2, which can be found in most op amp data sheets. Equation 2 gives the compensation voltage referenced to the op amp input. By multiplying the result of Equation 2 by the op amp gain, the op amp output is referenced to the compensation voltage.

Because the op amp's PSRR further reduces small changes in the power supplies, you might incorrectly conclude that small changes in the power supply voltage have little or no effect in the system. As a quantitative example, we can analyze a fully differential op amp that buffers a signal to a 24-bit ADC.

Figure 3 shows a simplified schematic using a fully differential op amp, such as the OPA1632 , configured as a unity gain buffer to provide a signal to a 24-bit ADC, such as  the ADS1271 . The circuit is a simplified schematic of the ADC evaluation board. The op amp is powered by an LDO with 3% accuracy over line, load, and temperature. The output voltage of the LDO is configured for ±15V nominal.

Figure 3 Example circuit for calculating the effect of compensation error (click on image to enlarge)

If the output voltages of each LDO are exactly +15V and -15V respectively, then the common mode input voltage is exactly 0V. For this example, if zero volts are at their inputs, we read zero counts from the ADC. Then, with the supplies equal in magnitude and no signal at the op amp inputs, you would read zero counts from the ADC.

However, assuming the positive voltage LDO output increases by 3%, it is still within the LDO specification. Using a 15V output, this 3% change is equivalent to a supply voltage increase from 450mV to 15.45V. According to the datasheet, the typical PSRR of the op amp is 97dB.

Equation 2 can now be used to calculate the offset voltage at the op amp input. There is an additional 3.178μV offset voltage at the op amp input. Since the op amp is configured as a unity gain buffer, this 3.178μV is also present at the output and applied to the ADC. The full-scale input range of the ADC is ±2.5V, so each ADC bit is equivalent to 298nV.

Using the compensation voltage generated by the power supply, the ADC now reads 11 counts instead of zero counts. The power supply introduces a DC compensation error in the counts read by the ADC. This error varies with the LDO output voltage, which varies with time, temperature, load current, and input voltage. This makes this error difficult to calibrate out and makes the lower four bits of the ADC uncertain.

A simple way to improve the tracking and accuracy (or drift) of an LDO is to modify the circuit of Figure 2 to that of Figure 4. The additional amplifier U1 and four resistors are required to configure for a gain of 2. The node between R3 and R4 should be at zero volts under nominal conditions. Therefore, the value of R1 must be equal to R2, and the value of R3 must be equal to R4.

Figure 4 Circuit with added tracking. (Click on the image to enlarge)

In Figure 2, the feedback network of each LDO is connected to ground. In Figure 4, the feedback resistors are connected to ground and driven by the output of U1. Now, if any power supply changes its output voltage, the difference appears at the non-inverting input of U1 and is gained up by a factor of 2. Since the output of U1 drives both LDO feedback networks, both LDOs are corrected to force their outputs to be equal.

It is important to note the circuit shown in Figure 4. The output of U1 can be driven to a voltage close to or equal to the power rails that power U1. If U1 is powered with ±18V from the input source, the output can be driven up to 18V. This 18V output is applied to the feedback pin of the LDO, which may exceed its absolute maximum voltage rating. Clamping diodes can be added to protect the LDO feedback pin under high dynamic load conditions of the LDO, short circuit conditions, or during power-up.

The schematic of the LDO with the tracking circuit and protection diodes added is shown in Figure 5. To make the schematic easier to understand, the 10 μF bypass capacitors for each power rail of U3 have been removed.

Figure 5 LDO tracking circuit with voltage protection

The circuit shown in Figure 5 uses an   adjustable, negative output voltage LDO linear regulator  such as the TPS7A3001 , and an adjustable, positive output voltage LDO such as the TPS7A4901  . U3, R7-R10, and C3 are all added components for tracking. R1, R2, D1-D5 are all added components to control the voltage at the feedback pin to within the absolute maximum voltage range specified in their respective datasheets.

All other components are typically required to support the LDO, such as input and output capacitors and feedback resistors. The LDO shown can support an input voltage range of ±36V, but the input voltage of this circuit is reduced to ±22V due to the recommended voltage limit of the TLE2141  op amp. A higher voltage op amp can be selected to cover the full ±36V input range of the LDO.

In both LDO feedback control schemes, the tracking circuit forms an additional voltage loop. The bandwidth of the added op amp U3 needs to be reduced by C3 to maintain system stability. U3 bandwidth needs to be at least 1/10 of the lowest LDO voltage loop. This means that U3 will typically only have a bandwidth of a few kilohertz. Therefore, it will not add to the high frequency PSRR of the system. The PSRR of the LDO primarily determines the high frequency PSRR of the system.

Summarize

This discussion clearly shows how the DC bias supply affects some of the performance parameters of an op amp. Using the equations provided in this article, the magnitude of these effects can be measured and calculated to determine their impact in an analog system. You can also learn that adding some additional components to build a tracking supply for an op amp can reduce the amount of input offset voltage, establish the correct sequence to reduce the occurrence of latch-up problems, and improve the overall voltage accuracy of the linear regulator used for the op amp DC bias supply.