C6678 power-on timing analysis

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C6678 power-on timing analysis [Copy link]

The power-on timing of C6678 is shown in the figure below. The timing analysis is as follows:
1. All power supplies and clocks are stable (RESET, POR, and RESETFULL signals are initially low).
2. Pull up the RESET signal
. 3. After pulling up RESET, the POR signal is kept for at least 100us before being pulled up.
4. Keep the GPIO pin status valid for 2ms and then pull up RESETFULL. Continue to keep the GPIO pin status valid for 2ms.
5. Finally, the RESETSTAT signal will be pulled high (this signal is driven and output internally by the chip).
Power-on timing