Design and simulation study of 0.18μm H-gate P-Well SOI MOSFET device

1. Introduction

In recent years, a new round of space exploration has emerged worldwide, and major space powers in the world have successively introduced a series of ambitious space development plans. The rapid development of space technology has made various electronic devices widely used in artificial satellites, spacecraft and other equipment. In the natural space radiation environment, they often suffer from space radiation, resulting in performance degradation or failure, and even eventually leading to catastrophic consequences for satellites or spacecraft. Therefore, radiation-resistant electronic components must be used in electronic equipment in harsh radiation environments.

Compared with bulk silicon devices, the unique insulating layer of silicon on insulator separates the device from the substrate, reduces the influence of the substrate on the device, reduces the source-drain capacitance, eliminates the latch effect, improves the short channel effect and hot carrier effect, improves the radiation resistance, etc. Therefore, SOI technology can be successfully applied in the field of radiation resistance, and it is internationally recognized as the "silicon integrated circuit technology of the 21st century". The comparison of the structure of SOI and bulk silicon MOS devices is shown in Figure 1.

Generally, SOI is divided into thin film fully depleted FD (Fully Depleted) structure and thick film partially depleted PD (Partially Depleted) structure according to the thickness of silicon film on insulator. The SOI MOS device designed in this paper is a thin film fully depleted structure, because the thin film SOI structure device completely eliminates the "warping effect" due to the full depletion of silicon film, and this type of device has the advantages of low electric field, high transconductance, good short channel characteristics and near ideal subthreshold slope. Therefore, thin film fully depleted FDSOI should be a very promising SOI structure.

Therefore, it is of great significance to study SOI MOS devices. This paper will design a 0.18μm H-gate P-Well SOI MOS device and simulate the electrical characteristics of the device, and obtain two important parameters, threshold voltage and saturation current, through simulation.

2. Design of 0.18μm H-gate P-Well SOI MOSFET

The entire design process is: first, use the Sentaurus Structure Editor tool to edit the basic structure of the device and set the type and dose of the implanted particles; then, use the mesh generation tool Mesh in the Sentaurus Structure Editor tool to set the mesh parameters of the device; finally, use the Sentaurus Device tool to simulate the electrical characteristics of the device and test it. In this section, I will use the above process to design a 0.18μm H-gate P-Well SOI MOSFET device.

For the design of the device structure, the X-axis and Y-axis ranges of the device structure are [-0.3, 0.3] and [-0.3, 0.3] respectively, and the Z-axis range is the sum of the thicknesses set in the following process.

First, draw a 0.2μm thick silicon substrate, draw a 0.15μm thick insulating oxide layer on the silicon substrate, and then draw a 0.1μm thick silicon layer (i.e., top silicon layer) on the insulating oxide layer; then, place a 0.005μm thick oxide layer on the top silicon, and place a polysilicon gate layer with a width of 0.18μm and a thickness of 0.04μm on the oxide layer; finally, place sidewalls around the gate and define contact points.

After the above process, the basic structure of the device has been completed. Next, inject boron particles with a dose of 1E+11cm-3 into the top silicon to form a P-Well. Before injecting particles into the source and drain, it is necessary to define the particle injection window, and then set the injection particle type, peak dose, peak position and diffusion length. The source and drain injection particle parameters are shown in Table 1.

The device structure and some parameters of doped particles have been set. Now we need to set the grid. Here we set three parts of the grid, the global grid, the grid of the top silicon layer, and the grid at the channel. The grid at the channel is set because when simulating the electrical characteristics of the device, the transmission of particles is mainly in the channel. Setting a reasonable grid at the channel will not only improve the simulation accuracy, but also optimize the simulation speed.

After setting up the grid, you can integrate the device structure, doping information, and grid information into a grid file by generating the grid. This file is needed when simulating the electrical characteristics of the device.

The simulation of the electrical characteristics of a device can be understood as a virtual test of the electrical characteristics of a semiconductor device (for example, a transistor or a diode). The device is considered as a structure composed of finite grid points, and each point in the structure contains properties such as metal type, doping particle type and concentration. For each point, the carrier concentration, current density, electric field strength, generation and recombination rate of electron-hole pairs, etc. must be calculated.

3. Results and Analysis

The structure and device characteristic simulation of the 0.18μm H-gate P-Well SOI MOSFET device are shown in Figures 2 to 7. The INSPECT tool is used to display the device electrical characteristic curve, and the TECPLOT_SV tool is used to display the device structure. Both tools are in the Sentaurus TCAD software.

Figures 2 and 3 show the device structure before and after the mesh is generated. The patterned interfaces shown in the figure represent the contact points of the source, drain, gate, and substrate. These contact points are used to set voltage parameters for device characteristic simulation. The concave areas in the figure are the source and drain, and the convex areas are the H-shaped gate. From top to bottom, the three layers below are the top silicon, insulating oxide layer, and substrate.