Implementation of Center-Aligned SVPWM for 3-Phase 3-Level Inverter

1 Introduction
SVPWM is widely used in 3-phase inverter control systems because it has a higher DC side voltage utilization efficiency than sinusoidal pulse width modulation (SPWM). Although SVPWM has many advantages, it is difficult to implement. The most difficult factor is to calculate the duty cycle of each power switch and determine the vector sector and pulse sequence for each switching cycle. Many articles have introduced the duty cycle calculation method of 3-phase 2-level inverters, and we can use many methods to calculate the vector sequence (for example, the center alignment method, which can be easily implemented in the MCU platform).

In order to improve the system efficiency of 3-phase inverters, 3-level or multi-level inverters are becoming more and more popular. Compared with 2-level inverters, 3-level inverters have more power switches (up to 12); this means that 3-level inverters have more vector sectors than 2-level inverters. Therefore, the duty cycle calculation and vector calculation of SVPWM for 3-level inverters are more complicated than those of 2-level inverters.

This article [1] introduces a simple method for calculating the vector sector. The calculation process has only two steps in total. The first step is to divide the entire vector into 6 main sectors. This step is very similar to the sector calculation method for a 2-level inverter. In step 2, the reference sector is relocated to one of the six sectors, and then this main sector is divided into six sub-sectors. This calculation method can be used for a 2-level inverter to determine the active vector and calculate its dwell time. However, we have not discussed the vector sequence for each switching cycle, and the duty cycle calculation method is difficult to implement in MCU applications. This paper [2] uses the same method to calculate the vector. The relocated zero vector is used as the zero vector of the 2-level inverter, and the resulting vector sequence is the same as that of the 2-level inverter. In the implementation, the MCU is used to generate the sequence signal and the peripheral logic circuit is used for the implemented PWM generation of each power switch. We have not introduced the method that does not have peripheral logic circuits and is suitable for MCU implementation. The

most effective method for SVPWM MCU implementation is center-aligned PWM, because the PWM module of the MCU can easily generate center-aligned PWM. This paper will discuss the SVPWM implementation based on the methods described in [1] and [2] and introduce a simple method to implement center-aligned SVPWM, which is suitable for on-chip PWM modules.

2 Basic SVPWM Schematic of a 3-Phase 3-Level Inverter
Figure 1 shows the hardware topology of a neutral point clamped (NPC) type 3-phase 3-level inverter.
 

Figure 1 Hardware topology of NPC 3-phase 3-level inverter

In Figure 1, there are three NPC legs (R, S, and T); each leg includes four power switches. The four power switches of each leg must be controlled in two compensation pairs. Qx1, Qx3 (x = R, S, T) is one compensation pair, and Qx2, Qx4 is another pair. Therefore, for each leg, it can output three different phase voltage states through four power switches.
 
Table 1 Output state of each leg

There are 27 states when controlling the power switch of each leg (see Table 1); each state can be mapped to a vector diagram in the α-β coordinate plane. The 27 vectors can form 18 sectors, as shown in Figure 2.
 

Figure 2 3-phase 3-level inverter SVPWM vector diagram

Assume a reference vector Vref. According to the SVPWM theory, we must find the two closest vectors Vx, Vy and a zero vector Vz in Figure 2 to form the vector Vref. Figure 2 shows the relationship between Vref and Vx, Vy, Vz. Therefore, we can select vectors PNN (Vx), PNN (Vy) and NNN (Vz) to form Vref. If the dwell time of Vx, Vy, Vz within the specified interval Ts is Tx, Ty, Tz respectively, the following function can be obtained:
 
However, it is still difficult to determine Vx, Vy, and Vz only by the angle used in the 2-level SVPWM, because the reference vector can be located in different sectors even if the angle is the same. In order to determine the sector, the size of the reference vector is required, but it will increase the complexity of the calculation method.

[1] and [2] introduced a simple method for calculating Vx, Vy, and Vz. First, the entire vector diagram shown in Figure 2 is divided into 6 main sectors. Each main sector contains 10 original sectors, which form a sub-hexagon. The 6 main sectors are continuously distributed with an angle difference of 60 degrees. Figure 3 shows the 6 main sectors.

 
Figure 3 Main sector of 3-level SVPWM

Given a reference vector Vref, the main sector can be calculated using only this angle. For example, in FIG4 , the angle θ between Vref and the α axis is +60 degrees to -60 degrees, which means that the main sector of Vref is sector 1.
 

Figure 4 Main sector 1

After calculating the main sector, it must map the initial vector to the selected main sector. The mapping algorithm is as follows:
 
For example, the initial vectors of the main sector 1 are PPP (OOO, NNN), POP (NON), PNO, PNN, PON, PPO (OON), POO (ONN). In order to obtain a hexagon similar to the 2-level SVPWM, POO (ONN) is used as the mapping vector Vmap1 = V0. After mapping, we can get the hexagon shown in Figure 5, which is the same as the vector diagram of the 2-level SVPWM. In this hexagon, there are 7 mapping vectors, which form 6 sub-sectors in the hexagon.
 

Figure 5 Main sector 1 mapping

From Figure 5, we can see that Vref is in sub-sector 1, and we can easily calculate the pause vectors as V1 and V2. V0 can be used as the zero vector of the 2-level SVPWM. Therefore, we can get the following function:
 
Combining equation (2) and equation (3), we get:
 
therefore
 
From equation 4, if the dwell time can be calculatedand, the initial vector dwell time can be calculated. By mapping in Figure 5, the vector selection and dwell time calculation of the 3-level SVPWM are completely converted to the 2-level SVPWM. Different main sectors have different mapping vectors. Table 2 summarizes the mapping vectors for each main sector.
 
Table 2 Mapping vectors for each main sector

3 Simple method for calculating the main sector
The main sector can be calculated using the Vref angle in the α-β coordinate plane. As shown in Figures 2 and 3, each main sector is within a fixed angle range. For example, the angle range of the first main sector isThe angular range of the second main sector can also be calculated asTherefore, the overlapping area between the first and second main sectors will extend to two adjacent areas. These overlapping areas increase the difficulty of calculating the main sectors. In order to specify the exclusive angle area of ​​each sector, we can redefine the main sectors, as shown in Figure 6.
 

Figure 6 New definition of primary sector

Using the definition shown in Figure 6, each main sector has its own angle area and its own sub-sector.

Considering the 3-phase voltage waveforms shown in Figure 7, the corresponding main sectors are marked at the correct position. From Figure 7, Table 3 summarizes the relationship between the main sector number and the 3 phase elements, which can help to easily determine the main sector.
 

Figure 7 Main sector location

 
Table 3 Primary sector determination method

4 Sub-sector process
In 2-level SVPWM, the first step is to find the sector number that can determine the dwell vector. The second step is to calculate the dwell time of each selected vector. According to the 3-level SVPWM principle in Chapter 1, when the main sector is determined and all vectors are mapped to the main sector, the same process as 2-level SVPWM can be used to determine the sub-sector and calculate the dwell time of each dwell vector. This process algorithm has been introduced in many articles, so this article will not discuss the sub-sector determination method and the dwell time calculation method.

Although we can find the dwell time of each vector through the sub-sector method, the duty cycle distribution of each power switch is much more complicated than that of 2-level SVPWM. 3-level SVPWM has 6 pairs of compensation power switches, which means that when we get the dwell time of the selected vector, 6 duty values ​​must be calculated. In order to simplify the duty cycle calculation process, this article introduces an effective method for easily calculating the duty cycle of each pair of power switches.

We also take the main sector 1 as an example. According to Figure 4, there is no N state in the R phase. In addition, if OON, ONO, and OOO are selected for vector mapping, there is no P state for the S and T phases. For the R phase, the P state is replaced by 1, and the O state is replaced by 0. For the S and T phases, the O state is replaced by 1, and the N state is replaced by 0. The result is the same vector diagram as the 2-level SVPWM. Figure 8 shows this operation process.
 

Figure 8 Status Replacement

After completing the 2-level SVPWM process, the pauses of the three vectors can be known. As shown in Figure 8, Tx is a 100 pause time, Ty is a 110 pause time, and Tz is a 111 and 000 pause time. Therefore, we can use the center-aligned PWM output mode to calculate the three duty cycles (d1, d2, and d3) of the three pairs of compensation power switches; the vector sequence obtained in this example is 000→100→110→111→110→100→000. The left side of Figure 9 shows the state of the upper switches of the three pairs of compensation power switches in the 2-level SVPWM, which is called center-aligned SVPWM.
 

Figure 9 2-level inverter center-aligned SVPWM

If we replace 1 and 0 with P and N respectively, we can get the right part of the 3-level inverter center-aligned SVPWM. The vector sequence of the 3-level SVPWM is:

ONN→PNN→PON→POO→PON→PNN→ONN.

The positive power switch pair is Qx1 and Qx3 (x = R, S, T); the negative power switch pair is Qx4 and Qx2 (x = R, S, T). Our definition of each pair of states 0 and 1 is also the same as the 2-level SVPWM. Therefore, for the main sector 1, in a single switching cycle, the negative R phase pair is always 0, and for the S, T phase, the positive pair is always 0. Then, only 3 pairs of power switches must be controlled by different duty cycles, positive R phase pairs and negative S, T phase pairs, which is equivalent to the 3 pairs of power switches of the 2-level SVPWM. This means that in the main sector 1, d1 can be assigned to the positive R phase pair, d2 can be assigned to the negative S phase pair, and d3 can be assigned to the negative T phase pair. The

previous analysis results can be extended to other vectors. Table 4 summarizes the state replacement, and Table 5 lists the duty cycle allocation for each master sector.
 
Table 4 State replacement for each master sector
 
Table 5 Duty cycle allocation for each main sector

5 Algorithm Implementation
Based on the analysis in Section 4, we can implement the 3-level SVPWM algorithm. Figure 10 shows the software flow chart.
 

Figure 10 3-level SVPWM algorithm flow chart

In Figure 10, all function inputs are the αβ elements of the reference vector.

RevParkConv is the function of the Park inverse conversion, from which we can get 3 phase static elements.
MainSectorCal is the function that determines the main sector number through the results listed in Table 3.

MapVector is the function that maps the reference vector to the selected main sector. Table 2 lists the mapping vector αβ elements.
Svgen_dq_2_Level is the function that implements the 2-level SVPWM process, from which we can know the three duty cycles d1, d2 and d3.

DutyAssign is the function that assigns CMPR values ​​to the power switch pairs through the results listed in Table 5.

6 Simulation Results
In order to test the effectiveness of the algorithm discussed in Chapter 5, we use Matlab Simulink Platform to obtain simulation results. All algorithms are completed through C code s functions, which can be easily ported to real systems.

The simulation conditions are as follows:
    Three-phase three-level NPC bridge
    switching frequency: 10kHz, PWM cycle count: 3000
    DC side voltage: 700V
    Reference phase-to-phase voltage: (1) 200 V/50 Hz; (2) 280 V/50 Hz
    LC filter parameters: Each phase, L = 9mH, C = 4.7μf
    R load: 100Ω per phase
    without dead time

 
Figure 11 Simulation results

(CH1: reference voltage; CH2: output voltage; CH3: main sector calculation; CH4: sub-sector calculation)

 

Figure 12 Simulation results

(CH1: positive QR1 PWM; CH2: negative QS2 PWM; CH3: negative QT2 PWM; CH4: main sector)
 

Figure 13 220Vac output CMPR values

​​CH1: R phase positive (blue) and negative (green) CMPR values
​​CH2: S phase positive (blue) and negative (green) CMPR values
​​CH3: T phase positive (blue) and negative (green) CMPR values

CH4: Main sector
 
Figure 14 280Vac output CMPR values

​​CH1: R phase positive (blue) and negative (green) CMPR values
​​CH2: S phase positive (blue) and negative (green) CMPR values
​​CH3: T phase positive (blue) and negative (green) CMPR values
​​CH4: Main sector

The simulation results shown in Figures 11 to 14 show that the algorithm is correct. This algorithm can be used to implement a 3-level 3-phase inverter SVPWM. However, since the effects of dead time and DC side voltage imbalance are not considered, further research is required. Therefore, we must pay special attention to the limitations of this method.