How do engineers debug digital hardware designs?

　　One of the most exciting moments in an engineering design project is when the hardware is first moved into the lab ready to begin integration testing. This phase of the development process can often take a long time and be very stressful for all project engineers. However, tools and methodologies exist to reduce stress and help projects move forward.

　　Let’s look at how to minimize any issues that may occur as you move your design to the next level and get through the debugging phase quickly and smoothly.

　　Imagine how you will test from day one

　　All engineers know that the cost of fixing problems increases as the development process progresses. Once the design is finalized and put into production, the cost of fixing pin-out errors will inevitably be higher than the cost of fixing them during early design evaluation. In addition, there are also cost issues in testing and integration. The earlier you consider testing issues for hardware, FPGAs, systems, etc. and write test specifications, the easier it will be for the engineering design team to consider the necessary test points, connections, and functionality. The purpose of testing is to ensure that a safe system can be launched that meets the specific requirements of the user. Therefore, we must ensure that the test can reflect all requirements, and functional testing requires that the process should be able to achieve process transfer and traceability of design requirements (that is, each test should meet its corresponding requirements).

　　It is also a good practice to edit the design verification model to detail the approach to testing each functional requirement, such as specific tests, analyses, or readouts (if the requirement was identified or tested earlier on another project). The document (Figure 1) may also include which tests are required for design verification and which are required for production operation. Completing this document early in the project phase ensures that the system design team and the test equipment design team have a clear basic approach.

　　However, before functional testing, designers must also ensure the correctness of the underlying hardware. They typically require hardware-level test specifications that include power, performance, and basic hardware verification, which is performed before functional testing.

　　It is very important to clarify what kind of test equipment is needed and what kind of performance it has. For example, do you need to analyze whether the signal generator and logic analyzer can provide sufficient memory depth and operating frequency? In addition, it is also necessary to clarify whether more specialized test equipment is needed, such as arbitrary waveform generators, high-stability frequency references, etc.

　　What should be included in the design phase

　　During the hardware design process, several design features and functions should probably be included to make the board easier to test. The requirements may be relatively simple or more in-depth.

　　The simplest and most common test rule is to place test points on all voltage sources, which avoids the possibility of damaging solder joints when probing them. However, a better approach is to place a pad connected to the ground (0V) return close to the voltage test point to simplify testing. If this test point is protected with a high value resistor, the current can be limited in the event of an accidental short circuit during testing. We can also consider adding test pins to these pads to connect to an automated test system that can then record the results during a production run. In addition, the ability to monitor the clock and reset outputs is critical. Therefore, placing a test point on the reset line is a good idea. Also, ensure that unused clock buffers are properly terminated and add test points to facilitate interrogation of the clock. Also consider adding test ports to enable signal injection and extraction through a signal generator, logic analyzer, or other test tools.

　　To help prototype power requirements, it is usually a good idea to add a low value resistor (10 milliohms, 100 milliohms, etc.) in series with the output of the voltage regulator, if possible, to accurately measure the current on the power rail.

　　Many FPGA devices also provide a method to monitor the chip temperature using a thermal diode. We need to find a way to provide a constant current to the diode. Measuring the chip temperature helps us ensure that the junction temperature does not exceed the rated value.

　　Make sure all components are in place and meet the design requirements, especially if only one pull-up or pull-down resistor should be in place and select the configuration mode.

　　After checking the components on the PCB , the next step is to apply power to the board for the first time. This is a very nervous moment for any engineer. However, the test provisions compiled during the design phase (test points, current sensing resistors, etc.) will be of great help at this time. The first step is to ensure that the power output of the load point and other regulators is not shorted back. You may find low impedance on the power rail with loaded devices (with high current requirements), but the impedance should be greater than 1 ohm.

　　For first-of-its-kind designs (i.e., the first time a new product is actually built), we may want to make further design decisions, such as separating the power supply from the downstream electronics. This way, we can ensure that the power supply and power-up sequencing are working properly, thereby avoiding overstressing or damaging downstream components. Another example of how a more detailed front-end design phase can help with testing is to ensure that the JTAG port can be used for more than just programming all FPGAs or processors in the system, such as initial hardware verification through boundary scan testing. Boundary scan testing is very useful for reducing hardware design risks early in the testing phase and also requires that the design be optimized to ensure maximum coverage of boundary scan devices.　　Define Hardware Features

　　When a system first arrives in the lab, the first thing you do is determine if the underlying hardware module is suitable for further testing. This includes an initial power-up test of the module, which is an intense process. The module has just arrived and you want to make sure it is accurate for production and will successfully power up for the first time. The first step is to make sure all components are in place, pin "1" is correctly oriented, and any components with polarity are accurately placed. Often a design may contain many components whose positioning does not need to be checked, such as those for different versions or different build options.

　　If you are sure that none of the rails are shorted, then the next step is to power up. When doing an initial power up, I tend to use a two-stage approach. The first stage is with low voltage (0.5V) and low current to ensure that you do not miss any shorts between signal layers or voltage rails; the second stage is to power up with the correct operating voltage within the set current limit to see if you get the expected current (don't forget the inrush current issue).

　　After successfully powering up the design, the next step is to determine if the power sequencing, resets, and clocks work as expected. Remember to ensure that the reset duration exceeds all clocks and is stable before releasing.

　　The next step in characterizing the hardware is to ensure that the hardware can be seen through the JTAG chain, which allows us to not only program the FPGA, but also perform boundary scan testing. Boundary scan testing allows us to quickly test the interconnections between devices, test the memory to ensure that it is working properly, and also loop back inputs and outputs if a loopback connector is developed. JTAG and boundary scan testing can eliminate design risks before further detailed testing.

　　Committed to simplifying RTL

　　If your design is complex at both the hardware and FPGA levels, a simplified version of the RTL will help test the development board and the interface between the FPGA and peripherals (Figure 2). This is especially true for high-speed interface designs. We can use optimized RTL with the Xilinx ChipScope tool to capture data and BlockBRAM preloaded with data patterns to stimulate. This approach is particularly useful when using ADCs and DACs to interface with the FPGA. In this case, you should take advantage of the reprogrammable nature of the FPGA to maximize the design development and implement parameter testing of the ADC and DAC, such as noise/power ratio, spurious-free dynamic range, and effective-number-of-bit calculations.

　　In addition, you should also make full use of the resources provided by the FPGA, especially the Xilinx SystemMonitor and XADC, which are very helpful for monitoring the voltage rails on the chip, which can also help verify the power integrity analysis performed during the design phase. In addition, the above techniques can also easily report the chip temperature, which is helpful for environmental testing and correlating power consumption with chip temperature.

　　In many cases, simplifying the RTL design and using the resources provided by the FPGA can greatly help pinpoint areas that are not working as expected.

　　What to do if you encounter problems?

　　As you progress through your testing program, you may encounter a problem or two where the expected functionality is not achieved or the required performance level is not met in a functional area. Don’t worry, we have many investigation methods to determine the root cause of the problem and the corrective actions required.

　　In the above cases, do not rush to make changes immediately. First, recheck the design, especially the design information such as schematics and data sheets. If the problem is related to the FPGA, check whether the pin constraint file is suitable for the design needs, because it is possible that the file is out of sync with the design.

　　If you can't find an obvious error, take advantage of the Internet and see if other engineers have encountered the same problem as you. There are many forums where you can ask other designers questions. Programmable Planet and the Xilinx Forums both provide extensive support for FPGA-based designs.

　　Ultimately, hardware debugging is a challenging, yet rewarding part of engineering design. If testing is considered early in the design process and the elements required for testing are included in the design, debugging can be greatly simplified. Using all available resources such as Chip Scope, System Monitor, and XADC to debug the system, combined with the proper use of traditional test equipment, we can successfully complete the development work.