Small CPLD has great wisdom and can be flexibly applied in high-frequency link inverter power supply

The 115V/400Hz power supply used in the aviation power distribution system is generally obtained by DC inverter, and is mainly used for military aircraft, radar and other equipment. The energy conversion process in the inverter power supply is that the DC power is converted into a high-frequency pulse voltage through the inverter circuit, and then forms a sine wave through the filter circuit. Recently, high-frequency link inverter technology has aroused more and more research interest. High-frequency link inverter technology uses high-frequency transformers to replace the bulky power frequency transformers in traditional inverters, greatly reducing the size and weight of the inverter. High-frequency link inverter technology was proposed by Mr. Espelage in 1977. The biggest difference between it and conventional inverter technology is that it uses high-frequency transformers to achieve electrical isolation between input and output, reducing the size and weight of the transformer.

The traditional high-frequency link inverter is composed of conventional digital circuits, which has the disadvantages of complex design and poor anti-interference ability. In order to solve this problem, this paper adopts complex programmable logic device (CPLD) to realize the design of control circuit. CPLD is an array-type PLD developed on the basis of PAL and CAL, which has the advantages of high density and high speed. This system uses the EPM7128SLC84-6 programmable device of Altera's MAX7000S series. The device adopts the second-generation multi-array matrix structure, the operating voltage is 5V, supports system programming, the operating frequency can reach 151.5 MHz, has 128 macro units, and the programmable extended product terms in each macro unit can reach 32. It has programmable encryption bits and can encrypt the design in the chip.

1 Main circuit structure of high frequency link inverter power supply

The traditional inverter power supply with isolation transformer consists of a high-frequency inverter, a rectifier, a PWM inverter and an output filter, requires three-stage power conversion, has the disadvantages of high conduction loss and can only transmit single-phase power.

Figure 1 shows the schematic diagram of a bidirectional voltage source high-frequency link inverter, which is a common solution for achieving bidirectional power transmission. The front-stage circuit consists of a full-bridge phase-shift control circuit and a high-frequency transformer, and the rear-stage circuit uses a frequency-converting AC-AC inverter. The high-frequency link inverter adopts a circuit topology of DC-high-frequency AC-low-frequency AC. The full-bridge phase-shift control circuit chops the DC voltage into a high-frequency pulse without a low-frequency component through a soft-switching ZVS method, and sends it to the frequency converter through a high-frequency transformer. The latter restores the high-frequency AC pulse to a sinusoidal pulse width modulation wave (SPWM) through a PDM method, and outputs a smooth sinusoidal wave signal through a low-pass filter. Because the inverter has only two-stage power conversion links and can achieve two-stage soft switching control, the switching frequency is very high (100kHz), so the efficiency is higher and the volume is smaller than the inverter using the sinusoidal pulse width pulse position modulation (SPWPM) method. 2 Control circuit and control strategy

The phase-shift converter of the previous stage adopts the most widely used soft switching circuit at present - phase-shift full-bridge zero voltage circuit (ZVS). Its principle is to use the resonance of transformer leakage inductance LIK and power tube output capacitor Gi. In the process of releasing leakage inductance energy to Gi, the Ci voltage gradually drops to zero, and the body diode Di is turned on, creating the ZVS condition of the switch tube. In order to change the duty cycle D and realize voltage regulation control, the phase-shift technology is adopted. The two switch tubes in each bridge arm are complementary and turned on. The conduction angles of the two bridge arms differ by a phase, that is, the phase shift angle. The output voltage is adjusted by adjusting the size of the phase shift angle. S1 and S2 are ahead of S3 and S4 by one phase respectively. The bridge arm composed of S1 and S2 is called the leading bridge arm, and the bridge arm composed of S3 and S4 is called the lagging bridge arm. By changing the control strategy of the switch tube, one of the switch tubes is turned off first, and the primary winding cooperates with the resonant capacitor to generate controllable dr/df. The leakage inductance and the output capacitor of the power MOSFET constitute a resonant network, and ZVS control is realized at the same time. The pulse operation sequence of the system is shown in Figure 2. After high-frequency inversion by the full-bridge phase-shift converter, a 100kHz adjacent pulse SPWPM (sinusoidal pulse width pulse position modulation) wave with opposite polarity is output. This waveform contains all the information of the SPWM wave, but does not contain the fundamental component of the 400Hz modulation wave, so it can be coupled and transmitted using a high-frequency transformer. The subsequent AC-AC cycloconverter uses pulse density modulation to modulate the high-frequency AC SPWPM wave into a conventional SPWM wave. The principle is that the output voltage waveform is synthesized by "piecemealing" the number or density of the input high-frequency discrete half-cycle pulses. The obtained 400Hz SPWM wave is filtered by LC, and a smooth 115V/400Hz sine wave is output.

3 CPLD) pulse trigger system working principle

The whole system adopts closed-loop control, and the control algorithm adopts repetitive control technology. The control algorithm is adjusted by DSP, and the timing and logic control of the driving signal is realized by CPLD.

The overall circuit diagram of the system is shown in Figure 3. The control circuit includes two parts: DSP and CPLD. The output voltage is fed back to the control circuit. The control circuit adjusts the trigger pulses of the front-end inverter circuit and the back-end frequency conversion circuit according to the given input. The implementation method of the inverter phase shift control circuit is relatively simple. Figure 4 is the implementation method of the phase shift control circuit, where Ve is a sawtooth carrier signal, and Vml and Vm2 are modulation signals. When the carrier signal is higher than the modulation signal, a high level is output; when the carrier signal is lower than the modulation signal, a low level is output. Since the switching frequency of the phase shift control is fixed and the duty cycle of the output signal is 50%, the rising edge of the V1- and V2 signals is used as the trigger signal, and the frequency is divided into two, then the drive signals vgs1 and vgs4 of the switch tubes S1 and S4 can be obtained, and the drive signals vgs2 and vgs3 of S2 and S3 can be obtained through the complementary relationship. The functions of this part are implemented by CPLD and obtained by Verliog programming.

In the voltage-type high-frequency inverter circuit, the commutation problem of the cycloconverter has become a difficult and key point in the research. The reason is that if the power tube is forcibly turned off to achieve commutation, a reverse electromotive force will be generated in the filter inductor. The generation of trigger pulses in the PDM control mode of the cycloconverter circuit is the focus of the research. It is difficult to achieve synchronization using traditional methods. CPLD is generally used for synchronization design, and the digital circuit in it can ensure accurate synchronization control. Its control logic block diagram is shown in Figure 5. In the figure, the synchronization signal is synthesized by the open loop of the phase shift control signal. Vgs1 represents the control signal of the leading bridge arm S1 switch, which is delayed by an angle of a1. The exclusive OR is to obtain the double frequency signal S1, "synchronized with S1, and then delayed by an angle of a2 to obtain Vk1, which is used as the clock signal of the D flip-flop to convert the conventional SPWM wave into a softened PWM wave. Vk1 is divided by two to obtain the vgs1 signal, which determines the switching moment of the bidirectional switch.

 4 System logic and timing function verification experiment

In this system, the CPLD development environment is MAXPLUSII, and Verliog is used to program the hardware. Figure 6 is a timing simulation waveform, where CLK is the CPLD system clock, vgs1 is the synchronization signal of the front-end inverter circuit and the back-end frequency conversion circuit, vgs1′ is the signal delayed by angle a1, vgs1″ is obtained by XORing vgs1′ and vgs1′, which is the clock signal of the D flip-flop, PWM is the modulation signal after softening synchronization, and vgs11 is the trigger pulse of the S11 switch tube. Among them, vgs1 and vgs1″ are not required to be output as output signals, but are listed for the convenience of simulation debugging.

Using the above main circuit structure and control method, a prototype with an output power of 350W, an output frequency of 400Hz, an output voltage of 115V, and a switching frequency of 100kHz was developed. Figure 7 shows the output waveform of the front-end phase-shifted full bridge. The test point is the secondary side of the high-frequency transformer, and the waveform is consistent with the principle waveform. Due to the leakage inductance of the high-frequency transformer, there is an oscillating voltage spike at the moment of opening.

Figure 8 is the output waveform of the inverter. Through two-stage LC filtering, the waveform harmonic distortion is very small and meets the index requirements.

5 Conclusion

It achieves high integration, high flexibility and has high reference value.