Pulse density power regulation high frequency inverter based on CPLD

At present, the output power adjustment of high-frequency induction heating power supply is mainly achieved by changing the output frequency of the inverter or changing the input DC voltage of the inverter. Changing the output frequency of the inverter to adjust the output power is a commonly used power regulation method. Its disadvantage is that the load of the inverter is inductive, especially when lightly loaded, the output power factor of the inverter is very low and the switching loss is large. This disadvantage can be changed by controlling the inverter to achieve power control. The pulse density modulated (PDM) DC/AC inverter uses the energy storage of the series resonant load and adopts the pulse group control method for the switch of the inverter. The output power is controlled by controlling the ratio (duty cycle) of the continuous on pulse signal and the continuous off pulse signal in one cycle. The traditional PDM implementation method is to use many counters and some PWM dedicated chips to achieve this. This method is stable and mature, but the control circuit is complex. Here, a method of using CPLD to achieve pulse uniform modulation is proposed. This method is simple and easy, with a short development cycle, simple circuit, small size, wide frequency tracking range, and the switch tube can operate in zero current shutdown (ZCS) and zero voltage switch (ZVS) states.

　　1 Circuit Structure

　　FIG1 is a main circuit diagram of a pulse uniformly controlled series resonant inverter power supply, which includes a three-phase uncontrolled rectifier circuit, a filter circuit, an inverter circuit and a series resonant circuit.

　　In Figure 1: C1 and L1 are filter capacitors and filter inductors; L0 is the load; D1, D2, D3, and D4 are anti-parallel fast diodes; T1 and T2 are current transformers; R2 and R3 are voltage-dividing resistors; VT1, VT2, VT3, and VT4 are IGBTs; C2 is a DC-isolating capacitor, and T0 is a load matching transformer.

　　Figure 2 is a block diagram of the entire control system, which uses CPLD as the main control chip, including frequency tracking circuit, drive circuit, detection circuit, and display part.

　　The three-phase power supply outputs a DC voltage through the rectifier circuit. The DC voltage is filtered and input to the inverter. The inverter realizes DC/AC conversion, and the generated AC power is output to the load through the transformer. The switch tube of the inverter is controlled by the control circuit composed of CPLD. The main control process is as follows: VT1 and VT4 are turned on at the same time, and the current passes through the load in the forward direction; VT2 and VT3 are turned on at the same time, and the current passes through the load in the reverse direction to realize DC to AC conversion. In order to make the inverter successful, it must be ensured that the switch tubes of the upper and lower bridge arms cannot be turned on at the same time, otherwise the inverter will fail, so a dead zone must be added when designing the switch control signal.

　　2 Pulse density control power principle

　　The basic idea of ​​density regulation power control is to assume that there are N power regulation units in total, in which the inverter outputs power to the load in M ​​power regulation units, and in the remaining (NM) units, the inverter stops working, and the load energy gradually decays in the form of natural oscillation, and the output pulse density is (M/N)%. The output power is regulated by controlling the IGBT in Figure 3 to make VT1, VT4 and VT2, VT3 work alternately. The principle is as follows:

　　The control signals of the switch tubes VT1 and VT3 are regarded as the sum of n 1/2i (i=1, 2, ..., n) frequency dividers, that is, there are 2n control pulses in one control cycle. When the switch tube is fully operational, that is, the maximum power is 2n/2n, when 1 pulse is removed and 2n-1 pulses are left, the power value is (2n-1)/2n; when m (m<2n) pulses are removed and (2n-m) pulses are left, the power value is (2n-m)/2n; when there is no pulse, that is, when m=2n, the switch tube is completely turned off, that is, the minimum power is 0. Controlling the combination of these n frequency dividers can control the output power of the inverter.

　　This design uses 4 frequency dividers, that is, n=4. Including 2-frequency divider, 4-frequency divider, 8-frequency divider, 16-frequency divider, through their different combinations to get 16 different power values, as shown in Table 1. Among them, 0 means off, 1 means on. The power value is 0 when it is fully off, and 1 when it is fully on. The power values ​​corresponding to the other combinations are shown in Table 1.

　　Figure 4 shows the control signal diagram when the power value is 1/16, 2/16, 4/16, and 8/16, and is also the principle diagram of 16-division, 8-division, 4-division, and 2-division. The control signals of VT2 and VT4 are the same at different power values. A brief description of the circuit working state is shown in Figure 4.

　　When VT1, VT4 are turned on and VT2, VT3 are turned off, the load resonant current is positive, and the load resonant current flows from a to b through VT1, R1, L2, C2, and VT4. The equivalent circuit is shown in Figure 4(a), and is powered by U.

　　When VT1, VT4 are turned off, VT2, VT3 are turned on, the load resonant current is negative, and the load resonant current flows from b to a through VT2, C2, L2, R1, VT3. The equivalent circuit is shown in Figure 4(b), which is powered by U.

　　When VT1, VT2, VT3 are turned off and VT4 is turned on, the load resonant current is positive. The load resonant current flows from a to b through R1, L2, C2, and VT4. The equivalent circuit is shown in Figure 4(c), and the current continues through D3.

　　When VT1, VT3, and VT4 are turned off and VT2 is turned on, the load resonant current is negative. The load resonant current flows from b to a through VT2, C2, L2, and R1. The equivalent circuit is shown in Figure 4(d), and the current continues through D1.

　　3 CPLD Implementation of Pulse Density Control Strategy

　　The Altera MAXⅡ EPM1270 chip is used as the platform, which includes 1 270 LEs, equivalent to 40 000 gates, 8 kB of user-available FLASH, and 116 I/O ports. QuartusⅡ5.1 is used for programming, downloading and simulation.

　　Figure 5 shows the logic module block diagram of CPLD pulse density control, which mainly includes pulse signal distribution control module, pulse distribution module, pulse width calculation and dead time setting module and PWM pulse width control module.

　　The pulse distribution module controls the pulse distribution module according to the power given value. The pulse distribution module consists of four frequency dividers: 2, 4, 8, and 16. It combines the frequency dividers according to the signal of the pulse distribution control module. The pulse width calculation and dead time setting module calculates the pulse width according to the input current signal, and controls the PWM output module to control the pulse width and set the dead time.

　　4 Simulation and Experiment

　　The following are some simulation and test diagrams of CPLD to achieve pulse density power control. In the simulation diagram, the signals from top to bottom are: enable signal, current input signal Iin, power given PWM1, PWM2, PWM3, PWM4 control signals, which control VT1, VT4, VT3, VT2 respectively. Figure 6 shows the simulation diagram when the power value is 8/16 and 16/16 with QuartusⅡ5.1 as the software environment. Figure 7 is the corresponding test waveform diagram downloaded to the Altera MAXⅡEPM1270 chip.

　　Figure 8 shows some experimental results of input power three-phase 220 V (phase voltage), frequency 50 Hz, output power P = 1 kw, resonant frequency f = 100 kHz, load equivalent inductance L2 = 26 μH, load equivalent resistance R1 = 6.5 Ω. The coordinate values ​​of the two waveforms are the same, the square wave is voltage, and the sine wave is current.

　　5 Conclusion

　　The strategy of using CPLD to realize pulse uniform modulation power control inverter is proposed here. CPLD undertakes the tasks of PWM generation, density adjustment and dead time control. Through current feedback, frequency tracking is realized, so that the inverter always works in a resonant state, improves work efficiency and reduces losses. The simulation and test results show the feasibility of this scheme. This scheme has the advantages of high reliability, can effectively reduce the volume of the control board, simple circuit, and easy to achieve high frequency.