Engineers explain PCB layout design tips for non-isolated switching power supplies

A good layout design optimizes efficiency, eases thermal stress, and minimizes noise and interactions between traces and components. All of this stems from the designer's understanding of the current conduction paths and signal flows in the power supply .

When a prototype power supply board is powered up for the first time, the best-case scenario is that it not only works, but does so quietly and cools the board. However, this is rarely the case.

A common problem with switching power supplies is "unstable" switching waveforms. Sometimes, the waveform jitter is in the acoustic band and the magnetic components can generate audio noise. If the problem lies in the layout of the printed circuit board, it may be difficult to find the cause. Therefore, correct PCB layout in the early stage of switching power supply design is very critical.

Power supply designers need to have a good understanding of the technical details and functional requirements of the final product. Therefore, from the beginning of the circuit board design project, power supply designers should work closely with PCB layout designers on critical power supply layout.

A good layout design can optimize power efficiency and ease thermal stress; more importantly, it minimizes noise and the interaction between traces and components. To achieve these goals, designers must understand the current conduction path and signal flow inside the switching power supply. To achieve the correct layout design of non-isolated switching power supplies, it is important to keep in mind the following design factors.

Layout Planning

For an embedded dc/dc power supply on a large circuit board, to achieve the best voltage regulation, load transient response and system efficiency, it is necessary to keep the power supply output close to the load device and minimize the interconnection impedance and conduction voltage drop on the PCB trace. Ensure good air flow to limit thermal stress; if forced air cooling can be used, place the power supply close to the fan.

In addition, large passive components (such as inductors and electrolytic capacitors) must not block airflow through low-profile surface-mount semiconductor components, such as power MOSFETs or PWM controllers. To prevent switching noise from interfering with analog signals in the system, sensitive signal lines should be placed under the power supply as little as possible; otherwise, an internal ground layer should be placed between the power layer and the small signal layer for shielding.

The key is to plan for the location of the power supply and the board space required during the early design and planning stages of the system. Sometimes designers ignore this advice and focus on the more "important" or "exciting" circuits on the large system board. Power management is treated as an afterthought, and power supplies are haphazardly placed on the board where there is extra space, which is detrimental to the design of efficient and reliable power supplies.

For multi-layer boards, a good approach is to place a DC ground or DC input/output voltage layer between the high-current power component layer and the sensitive small signal routing layer. The ground layer or DC voltage layer provides an AC ground to shield the small signal routing from interference from high-noise power routing and power components.

As a general rule, the ground or DC voltage layers of multi-layer PCBs should not be separated. If such separation is unavoidable, the number and length of traces on these layers should be minimized, and the traces should be laid out in the same direction as the large current to minimize the impact.

Figures 1a and 1c show the bad layer structures of six-layer and four-layer switching power supply PCBs, respectively. These structures sandwich the small signal layer between the high current power layer and the ground layer, thus increasing the capacitive noise coupled between the high current/voltage power layer and the analog small signal layer.

1b and 1d in the figure are good structures of six-layer and four-layer PCB design respectively, which help to minimize the inter-layer coupling noise. The ground layer is used to shield the small signal layer. The key point is: a ground layer must be placed next to the outer power stage layer, and thick copper foil should be used for the external high-current power layer to minimize PCB conduction loss and thermal resistance. Layout of the power stage

The switching power supply circuit can be divided into two parts: the power stage circuit and the small signal control circuit. The power stage circuit contains components for transmitting large currents. Generally, these components should be placed first, and then the small signal control circuit should be placed at some specific points in the layout.

High current traces should be short and wide to minimize the inductance, resistance and voltage drop of the PCB. This is especially important for traces with high di/dt pulse currents.

Figure 2 shows the continuous current path and pulse current path in a synchronous buck converter. The solid line represents the continuous current path and the dashed line represents the pulse (switching) current path. The pulse current path includes the traces connected to the following components: input decoupling ceramic capacitor CHF, upper control FET QT and lower synchronous FET QB, and the optional parallel Schottky diode.

Figure 3a shows the PCB parasitic inductance in the high di/dt current path. Due to the presence of parasitic inductance, the pulse current path not only radiates magnetic fields, but also generates large voltage ringing and spikes on the PCB traces and MOSFETs. To minimize the PCB inductance, the pulse current loop (the so-called hot loop) should be laid out with a minimum circumference and its traces should be short and wide.

High-frequency decoupling capacitors CHF should be 0.1μF~10μF, ceramic capacitors with X5R or X7R dielectrics, which have extremely low ESL (effective series inductance) and ESR (equivalent series resistance). Larger capacitor dielectrics (such as Y5V) may cause the capacitance value to drop significantly at different voltages and temperatures, and are therefore not the best material for CHF.

Figure 3b provides an example layout for the critical pulse current loop in the buck converter. To limit the resistance drop and the number of vias, the power components are placed on the same side of the board and the power traces are placed on the same layer. When a power line needs to be routed to another layer, a trace in a continuous current path should be selected. When vias are used to connect PCB layers in high current loops, multiple vias should be used to minimize impedance.

Figure 4 shows the continuous current loop and pulse current loop in the boost converter. In this case, a high-frequency ceramic capacitor CHF should be placed at the output end close to the MOSFET QB and boost diode D.

Figure 5 shows the hot loop and parasitic PCB inductance in a boost converter (a); the recommended layout to reduce the hot loop area (b)

Figure 5 is an example of a layout for the pulse current loop in a boost converter. The key here is to minimize the loop formed by the switch tube QB, the rectifier diode D and the high-frequency output capacitor CHF. Figure 6 provides an example of a synchronous buck circuit, which emphasizes the importance of decoupling capacitors. Figure 6a is a dual-phase 12VIN, 2.5VOUT/30A (maximum) synchronous buck power supply using the LTC3729 dual-phase single VOUT controller IC. When there is no load, the waveforms of the switch nodes SW1 and SW2 and the output inductor current are stable (Figure 6b). However, if the load current exceeds 13A, the waveform of the SW1 node begins to lose cycles. The problem worsens at higher load currents (Figure 6c).

This problem can be solved by adding two 1μF high-frequency ceramic capacitors at the input of each channel. The capacitors isolate and minimize the hot loop area of ​​each channel. Even at the maximum load current of up to 30A, the switching waveform is still stable. High DV/DT switching area

In Figure 2 and Figure 4, the SW voltage swing between VIN (or VOUT) and ground has a high dv/dt rate. This node has abundant high-frequency noise components and is a strong source of EMI noise. In order to minimize the coupling capacitance between the switch node and other noise-sensitive traces, you may make the SW copper area as small as possible. However, in order to conduct large inductor currents and provide a heat dissipation area for the power MOSFET, the PCB area of ​​the SW node cannot be too small. It is generally recommended to place a grounded copper area under the switch node to provide additional shielding.

If there is no heat sink for surface mounted power MOSFET and inductor in the design, the copper foil area must have enough heat dissipation area. For DC voltage nodes (such as input/output voltage and power ground), the reasonable approach is to make the copper foil area as large as possible.

Multiple vias help further reduce thermal stress. Determining the appropriate copper area for high dv/dt switching nodes is a design balance between minimizing dv/dt related noise and providing good MOSFET heat dissipation.

Power pad type

Pay attention to the pad pattern of power components such as low ESR capacitors, MOSFETs, diodes, and inductors.

For decoupling capacitors, the positive and negative vias should be as close to each other as possible to reduce the ESL of the PCB. This is especially effective for low-ESL capacitors. Small-value, low-ESR capacitors are usually more expensive, and incorrect pad forms and poor routing will reduce their performance, thereby increasing overall costs. Generally speaking, a reasonable pad form can reduce PCB noise, reduce thermal resistance, and minimize routing impedance and voltage drop of high-current components.

A common mistake when laying out high-current power components is the incorrect use of thermal relief pads. Using thermal relief pads when not necessary will increase the interconnect impedance between power components, resulting in greater power loss and reduced decoupling effects of small ESR capacitors. If vias are used to conduct high currents during layout, make sure there are enough of them to reduce impedance. Also, do not use thermal relief pads for these vias.

Keep the control circuit away from the noisy switching copper area. For a buck converter, it is a good idea to place the control circuit close to the VOUT+ terminal, and for a boost converter, the control circuit should be close to the VIN+ terminal, allowing the power trace to carry continuous current.

If space permits, there should be a small distance (0.5 inch to 1 inch) between the control IC and the power MOSFET and inductor (which are high-noise and high-heat components). If space is tight and you are forced to place the controller close to the power MOSFET and inductor, pay special attention to using ground layers or ground traces to isolate the control circuit from the power components.

The control circuit should have an independent signal (analog) ground that is different from the power stage ground. If there are independent SGND (signal ground) and PGND (power ground) pins on the controller IC, they should be routed separately. For control ICs with integrated MOSFET drivers, the IC pins of the small signal part should use SGND.

Only one connection point is needed between the signal ground and the power ground. A reasonable approach is to return the signal ground to a clean point in the power ground layer. Two grounds can be achieved by connecting the two ground traces only under the controller IC.

The decoupling capacitors of the control IC should be close to their respective pins. To minimize the connection impedance, the best method is to connect the decoupling capacitors directly to the pins without vias.

Loop Area and Crosstalk

Two or more adjacent conductors can produce capacitive coupling. High dv/dt on one conductor will couple current on another conductor through parasitic capacitance. To reduce the coupled noise of the power stage to the control circuit, the high-noise switching traces should be kept away from sensitive small signal traces. If possible, place high-noise traces and sensitive traces on different layers and use internal ground layers as noise shields.

If space permits, the control IC should be a small distance (0.5 inch to 1 inch) from the power MOSFET and inductor, which are both noisy and hot.

The FET driver TG, BG, SW and BOOST pins on the LTC3855 controller all have high dv/dt switching voltages. The LTC3855 pins connected to the most sensitive small signal nodes are: Sense+/Sense-, FB, ITH and SGND. If the sensitive signal traces are placed close to the high dv/dt nodes during layout, a ground line or ground plane must be inserted between the signal traces and the high dv/dt traces to shield the noise.

When routing the gate drive signals, using short and wide traces helps minimize the impedance in the gate drive path.

If a PGND layer is placed under the BG trace, the AC ground return current of the low FET will automatically couple into a path close to the BG trace. The AC current will flow to the smallest loop/impedance it finds. In this case, the low gate driver does not need a separate PGND return trace. The best approach is to minimize the number of layers that the gate drive trace passes through to prevent gate noise from propagating to other layers.

Among all small signal traces, current sense traces are the most sensitive to noise. The amplitude of the current sense signal is usually less than 100mV, which is comparable to the amplitude of the noise. Taking LTC3855 as an example, the Sense+/Sense- traces should be laid out in parallel with minimum spacing (Kelvin detection) to minimize the chance of picking up di/dt related noise.

In addition, the filter resistor and capacitor of the current detection line should be as close to the IC pin as possible. This structure has the best filtering effect when noise is injected into the long detection line. If the inductor DCR current detection method with R/C network is used, the DCR detection resistor R should be close to the inductor, and the DCR detection capacitor C should be close to the IC.

If a via is used on the return path of the trace to Sense-, the via should not touch other internal VOUT+ layers. Otherwise, the via may conduct a large VOUT+ current, and the resulting voltage drop may corrupt the current sense signal. Avoid routing the current sense traces near noisy switching nodes (TG, BG, SW, and BOOST traces). If possible, place a ground plane between the current sense trace layer and the power stage trace layer.

If the controller IC has differential voltage remote sense pins, use separate traces for the positive and negative remote sense lines and also use Kelvin sense connections.

Trace Width Selection

The current level and noise sensitivity are unique to the specific controller pins, so specific trace widths must be selected for different signals. Typically, small signal networks can be narrower, with 10mil to 15mil traces; high current networks (gate drive, VCC, and PGND) should use short and wide traces. The traces for these networks are recommended to be at least 20mil wide.